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Xelerated Touts 40-Gig Toolbox

Sweden's Xelerated AB (formerly Xelerated Packet Devices AB) today became the first 40-Gbit/s network processor company to launch part of its product package -- the development tools (see Xelerated Proffers Tools).

Many of the big chip makers such as Agere Systems (NYSE: AGR) and Applied Micro Circuits Corp. (AMCC) (Nasdaq: AMCC), have 40-Gbit/s network processors on their roadmaps, but are still struggling to roll out 10-Gbit/s solutions (see OC192 Processors: Who's First?). And other startups targeting 40-Gbit/s straight off, namely, ClearSpeed Technology Ltd. and Teradiant Networks Inc., appear to be behind Xelerated in their development.

Network processors are programmable chips that should give systems vendors an alternative to developing their own ASICs for packet processing. Software is very important, because the system vendor must now use the functions delivered by the software to differentiate its product, rather than building them directly into silicon.

The development tools allow the system vendor to build applications. In Xelerated's case, these tools comprise an assembler and linker for compiling the code, a simulator, which is used to debug the code, and a batch of sample applications, including MPLS, IPv4, and IPv6.

Xelerated says the tools are available immediately, although it has yet to close any deals with customers.

It's worth pointing out that Xelerated's network processor, the X40, will not be available until the summer, but having tools ready in advance of the actual silicon is a good idea because it allows potential customers to evaluate the product, says Xelerated's CEO Johan Börje. In addition, systems vendors can start developing applications for the target system as early as possible, thus speeding up time to market.

"Now, for the first time, customers can really evaluate the truth of what we've been communicating to them," he says.

"The truth," according to Börje, is that Xelerated's network processor has a very simple programming model. And that's no small thing.

In real life, many network processors have turned out to be total pigs to program, so system vendors haven't been any better off than they were when they had to make their own ASICs. Instead of spending loads of time and money developing ASICs, system vendors spend loads of time and money writing incredibly complicated programs in assembly code.

Most network processor vendors, including Agere and AMCC, figure that the way around programming prolixity is to offer a high-level programming language, which hides the complexity of the assembly language from the user.

But Börje contends it's a bit of a myth in the industry that a high-level language is the answer to all ills. "You will never construct a compiler that is so intelligent that it can optimize everything. You'll always have to go to a low level to fine tune -- tune with your hands, if you like."

In fact, Xelerated originally had a high-level language on its roadmap but has now satisfied itself that the assembly code is adequate. And, having seen that code, only one potential customer has still demanded to see a high-level language, Börje claims.

As noted, the reason the code is simple is because of the architecture. Xelerated uses what it calls a "multistage programmable pipeline" (see Swedes Claim Processor Advance). There are 200 stages in the pipeline, and on every clock tick, the packet moves on to the next stage, along with some context to tell subsequent stages how to deal with the packet. That means on every clock cycle, one packet goes into the processor and one packet comes out the other end.

Other types of network processor complete the processing of a single packet before they take in another. Since packets can be long or short, and instructions can be easy or difficult to execute, the length of time it takes to process a packet varies. As a result, the programmer has to decide how to balance instructions among different processor cores. And that's what complicates the programming procedure, Börje contends.

That may be the case, but there are other, compelling reasons to choose a high-level language, according to Robin Melnick, director of product marketing for AMCC's network processor group. First and foremost, it allows both the chip maker and the system vendor to protect their investment in software development. The system vendor can upgrade chips without having to rewrite the program. "From our perspective, we're not having to roll out a new software architecture and applications at the same time we roll out a new chip," he says.

Of course, this point is not necessarily relevant to Xelerated right now, which is jumping in feet first with 40 Gbit/s. But it could become so in the future.

— Pauline Rigby, Senior Editor, Light Reading
http://www.lightreading.com
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skeptic 12/4/2012 | 11:03:47 PM
re: Xelerated Touts 40-Gig Toolbox
Somehow I don't think a 200-stage pipeline
based processing system is going to turn out
to be easy to program. This is another case
of someone saying the right words, but probably
doing things completely wrong.
asmo 12/4/2012 | 11:03:46 PM
re: Xelerated Touts 40-Gig Toolbox
200 stages for their packet processor seems excessive, I wonder why they need this many.

With customized lookup, packet header manipulation hardware and on-chip assembly code you don't need 200 stages.

Interesting approach.

Asmo
xinant 12/4/2012 | 11:03:45 PM
re: Xelerated Touts 40-Gig Toolbox Please also consider some stages might be empty. i.e. nop must be inserted.

For simply IP and MPLS, 200 stages might be enough.
What happend if customs need L4-7 services such as
NAT?

Paul Andrews 12/4/2012 | 11:03:45 PM
re: Xelerated Touts 40-Gig Toolbox What does prolixity mean?
Pauline Rigby 12/4/2012 | 11:03:42 PM
re: Xelerated Touts 40-Gig Toolbox >Please also consider some stages might be empty.
>i.e. nop must be inserted.
>
>For simply IP and MPLS, 200 stages might be
>enough.
>What happend if customs need L4-7 services such
>as NAT?

I think I know the answer to this one.

According to Xelerated, when the chip comes out it will be running in 4 x 10 gig mode (non of the 40 gig interfaces or supporting chips are ready, so that makes sense). So there are four separate pipelines in the chip.

If 200 stages isn't enough, you can loop one of the egress ports back to the beginning of the chip, to create a pipeline that's twice as long. Or else you could tag on a second chip.

The behaviour will still be deterministic. But the more stages in the pipeline, the longer the latency, i.e. it now takes a packet twice as long to traverse the pipeline. Xelerated says that even with a 400 stage pipeline, the latency would still be less than 5 microseconds.

[email protected]
Confucius 12/4/2012 | 11:03:42 PM
re: Xelerated Touts 40-Gig Toolbox Prolixity means verbosity, so in context it means "requiring many programming steps".
skeptic 12/4/2012 | 11:03:39 PM
re: Xelerated Touts 40-Gig Toolbox For simply IP and MPLS, 200 stages might be enough.
What happend if customs need L4-7 services such as
NAT?
--------------

The customer is told that buying a 40 Gb/s
line card for processing NAT is silly and
that they should be doing that sort of thing
somewhere else in the network.


thomas.eklund 12/4/2012 | 11:03:24 PM
re: Xelerated Touts 40-Gig Toolbox Dear Pauline,

I would like to clarify on your statement. We only have ONE internal pipeline which schedules together the four 10 Gbps ports into the pipeline which means that it is a 40 G capable pipeline from day 1!! We only need to change the I/O to SPI-5 to have a 40 G clear channel solution.

-- thomas
lostinlight 12/4/2012 | 11:03:23 PM
re: Xelerated Touts 40-Gig Toolbox What is the point behind building 40Gpbs and upwards network processors? Is their target market backbone routers cards? How many chips do these companies aim to sell? a few thousands on the whole?
Are we going to witness a period when routers become commodity products and a couple of network processors playing main roles like Intel and AMD do today in the PC market?
skeptic 12/4/2012 | 11:03:22 PM
re: Xelerated Touts 40-Gig Toolbox What is the point behind building 40Gpbs and upwards network processors? Is their target market backbone routers cards? How many chips do these companies aim to sell? a few thousands on the whole?
------------
The point is that 40Gbps is the next level of
performance to be reached. Its too late for
10Gbps products (that cycle is over).

And what typically happens is that these companies
are sold to chip houses that want to be able to
sell a "full line" to potential customers.

And sure, the volumes are not going to be high,
but thats true of lots of specialty components.
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