The PSI2G100 combines a 2.5 Gbit/s serial link, 100k gates of programmable logic, and 0.5 Mbits of communications memory

April 3, 2001

1 Min Read

SAN JOSE, Calif. -- Cypress Semiconductor (NYSE: CY) today announced the availability of samples of the PSI2G100, the first in its family of Programmable Serial Interface (PSI™) chips. The PSI2G100 combines a 2.5 Gbps serial link, 100k gates of programmable logic, and 0.5 Mbits of communications memory, targeting system backplanes across a broad range of market segments, including InfiniBand™. PSI devices combine the flexibility, predictable timing, and ease-of-use of Cypress CPLDs with a SERDES, communications memory and phase-locked loops (PLLs). Cypress’s Warp™ software enables a seamless programming interface to allow design engineers to easily integrate custom IP with the SERDES via HDL blocks, HDL text, or graphical state machines. Cypress is the only company to offer a 2.5 Gbps SERDES, programmable logic gates, design entry, synthesis and verification in an integrated, single-chip solution.

“Cypress is delivering a programmable SERDES with all the advantages of our CPLDs: high speed, predictable timing, flexibility, ease of use, and non-volatility at leadership densities,” said Geoff Charubin, director of marketing for Cypress’s data communications division. “The PSI2G100 is precision tuned for custom backplane applications, giving communications solutions designers the ability to interface with their existing processors, ASICS and insert their own custom logic.”

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