Joins PMC-Sierra in unveiling Ethernet-over-Sonet mapper chips

January 7, 2002

3 Min Read
Agilent Boosts Ethernet-Over-Sonet

It’s not going to be Ethernet versus Sonet in metro networks; it’s going to be Ethernet over Sonet, judging by today’s announcement from Agilent Technologies Inc. (NYSE: A) (see Agilent's Got a Mapper).

Agilent has unveiled the first two members of a family of chips for funneling different types of traffic over Sonet connections. The first of these, HDMP-3001, takes in full-duplex Fast Ethernet (100 Mbit/s) line and maps it into an OC3c (155 Mbit/s) Sonet frame. The second chip, as yet unnamed, deals with full-duplex gigabit Ethernet, taking two streams of the protocol and mapping them into a single OC48 (2.5 Gbit/s) Sonet frame.

Agilent is following in the footsteps of PMC-Sierra Inc. (Nasdaq: PMCS), which announced similar chips last month (see PMC Pushes Sonet Silicon).

The availability of mapper chips from two big vendors could encourage equipment manufacturers to take the plunge with Ethernet-over-Sonet (EOS) additions to metro gear such as edge switches and add/drop multiplexers.

The standard behind the chips, called the "generic framing procedure" (GFP), is relatively new, notes Jim Shupenis, Agilent's director of strategic business development. "OEMs have offered EOS for some time, but they were forced to use proprietary solutions, which weren't interoperable with other equipment, even within the same company. Now, for the first time, we have standards."

With standards finalized, vendors of merchant silicon can start to offer solutions to a broad range of customers, he adds.

Agilent's chips also implement an older standard for encapsulation called LAPS (Link Access Protocol – SDH). Put simply, GPF is better than LAPS because it can support Sonet rings, while LAPS only handles point-to-point connections, Shupenis explains. "GFP does everything that LAPS does, but more so, because it's a newer standard. And the code is more efficient, which reduces the amount of time to execute instructions inside the processor."

The second, and more complicated, Agilent chip will also implement virtual concatenation (VC), a protocol that uses Sonet bandwidth more efficiently. VC makes it possible to provision Sonet in multiples of STS1 (58.4 Mbit/s), which wastes less bandwidth than using unwieldy OC3c or OC12c (622 Mbit/s) pipes.

The smaller chip, HDMP-3001, doesn't require VC because its main application is to transport the supervisory channel in-band, says Shupenis. It's carried in the space that's left over after packing a Fast Ethernet channel into an OC3c. According to Shupenis, right now most people running 10Base-T networks use a dial-up modem to call nodes on the ring in order to get this data, which is far less convenient.

Agilent's OC48 EOS mapper will compete directly with PMC's PM9537 ARROW-2xGE chip. And, although it was announced later, Shupenis claims it could ship before the PMC chip. Both Agilent's and PMC's products are slated to sample in the same timeframe, Q1 2002.

Agere Systems (NYSE: AGR) is also dabbling in GFP and VC. In October 2001, it released what it called "an add-drop multiplexer on a chip", which is a framer with integrated STS1 crossconnect that implements these protocols (see Agere Offers Single Chip ADM).

In the future, Agilent plans to extend its product family with chips that support other data types, including storage networking protocols iSCSI, Escon, Fibre Channel, and Infiniband.

— Pauline Rigby, Senior Editor, Light Reading

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