Zarlink Intros Analog Timing Chip

OTTAWA -- Zarlink Semiconductor (NYSE/TSX:ZL) today launched an analog timing chip with six low-jitter output clocks - more than any other competing product - for optical line cards. With Zarlink's highly integrated ZL30406 analog PLL (phase locked loop), designers can shrink the size, cost, and power of line card timing designs.

"Zarlink's ZL30406 device sets a new benchmark for integration, flexibility and performance in analog PLLs," said Louise Gaulin, product line director, Timing and Synchronization, Zarlink Semiconductor. "Coupled with the recent launches of our ZL30407 digital PLL for timing cards, and ZL30462 timing module for line cards, Zarlink is now the only company with a comprehensive range of analog, digital, and module timing and synchronization products."

Analog PLL devices perform critical timing and synchronization functions in communications equipment, including line cards used in SONET/SDH (Synchronous Optical Network/Synchronous Digital Hierarchy) access and metro equipment. Zarlink's ZL30406 analog PLL regenerates and multiplies clock signals - or reference frequencies - to higher frequencies, while also "cleaning up" jitter. Jitter is a short-term variation in clock timing that causes data errors in optical networks, particularly those operating at high speed.

"The ZL30406 device is the first SONET/SDH analog PLL to generate six low- jitter output clocks - the widest range of clocks in its class," said Darren Ladouceur, marketing manager, Timing and Synchronization, Zarlink Semiconductor. "The jitter performance of the device surpasses OC-48 and STM- 16 (Synchronous Transport Module level 16) requirements."

The ZL30406 chip delivers four differential LVPECL (low voltage positive emitter coupled logic) clocks at 77.76 MHz (megahertz); a differential CML (current mode logic) clock programmable to 19.44 MHz, 38.88 MHz, 77.76 MHz, and 155.52 MHz; and a single-ended CMOS (complementary metal oxide silicon) clock at 19.44 MHz.

The four differential LVPECL clock outputs interface directly to other devices on SONET/SDH line cards, including framers, mappers, and SERDES (serializer/deserializer) chips, reducing or eliminating the need for external glue logic circuitry. Glue logic - typically a range of fan-out and logic translation devices - adds cost, consumes power, and increases design footprints.

Along with the flexibility to select from different frequencies and logic formats, designers can enable or disable ZL30406 clocks as required, giving them a high degree of control.

The ZL30406 chip delivers ultra-low jitter performance of 0.46 picoseconds rms (root mean square). A picosecond is one trillionth of a second. This performance exceeds Telcordia's GR-253-CORE jitter requirements for OC-3 to OC-48 optical rates, and the ITU-T's (International Telecommunication Union-Telecommunications) G.813 Option 1 and 2 requirements for STM-1 to STM-16 rates.

Zarlink is the only company in the industry to provide digital PLLs, analog PLLs, and timing modules. The ZL30406 device can be used on its own, or in combination with one of Zarlink's digital PLLs, such as the MT9046 or ZL30407 chip, to provide an integrated, highly featured timing system with excellent performance.

Zarlink Semiconductor Inc.