Zarlink Deals OC3 Timing Chip

OTTAWA -- Zarlink Semiconductor (NYSE/TSX:ZL) today expanded its portfolio of timing devices for optical networking equipment with the ZLTM30410 digital PLL (phase-locked loop), a full-featured timing chip with the industry's lowest jitter, for access line cards operating at OC-3 (Optical Carrier level 3) rates. With the ZL30410 digital PLL and the company's analog PLLs for line cards, Zarlink is the first semiconductor company to offer both digital and analog timing devices for standards-compliant line cards in high-speed SONET/SDH (Synchronous Optical Network/Synchronous Digital Hierarchy) access systems. Zarlink's ZL30410 timing chip generates and synchronizes clock signals used by other line card devices, such as OC-3/STM-1 (Synchronous Transport Module level 1) framers, mappers, switches, and optical line interface chips. The company's analog PLLs connect seamlessly to the ZL30410, and support higher-speed applications by producing clock signals for OC-12/STM-4 or OC-48/STM-16 framers. "To handle rising traffic volumes at the network edge, access systems must operate at higher speeds, and that makes their timing circuitry more complex," said Michael Rupert, marketing manager, Timing and Synchronization, Zarlink Semiconductor. "Our digital and analog line card PLLs are fully tested for interoperability, which reduces complexity and makes it easier for designers to comply with stringent SONET/SDH network timing standards." Several global equipment vendors are evaluating Zarlink's line card chips for use in routers, multi-service access devices, DSLAMs (digital subscriber line access multiplexers), gateways, and next-generation DLCs (digital loop carriers). Zarlink Semiconductor Inc.