StarGen Claims PCIe, ASI Chip First
The AXSys architecture is comprised of a complementary family of ASI switches, ASI bridges, and a robust ASI fabric management software suite. OEMs who implement the AXSys architecture are guaranteed 100% compliance to the ASI 1.1 specification, full compatibility with PCI Express and future ASI-SIG defined endpoints, as well as the ability to fully implement the ASI-SIG fabric management software suite. Enabling rapid system development, the StarGen AXSys architecture also defines a number of development, performance testing, compliance, and interoperability tools. These include standalone ASI switch systems, PCIe endpoints, ATCA based platform development kits, and a number of software applications and development tools.
AXSys Architecture – first devices revealed
StarGen today also unveiled top level details of the first AXSys architecture compliant devices including the Merlin ASI Switch, and the Kestrel ASI to PCIe Host Bridge. During 2005, StarGen will be making a series of formal product and partner announcements surrounding further details of the AXSys family of devices, development tools, and system applications which are designed to help OEMs rapidly bring their systems and software to market with advanced capabilities.
ASI Switch – Merlin: Designed for use as an advanced interconnect in emerging standard backplanes such as AdvancedTCA or custom OEM hardware platforms, a single Merlin ASI switch has 80Gbps switching capacity with the architectural capability to cascade multiple devices together to support larger topologies and achieve aggregate system switching capacities up to 400Gbps. Merlin is configurable in various port widths to meet diverse system needs including ten 8.0 Gbps (x4) ports or five 16.0 Gbps (x8) ports. The switch also includes native bridging for PCIe I/O endpoints by incorporating PI-8 leaf bridging on all of its ports. This functionality allows each port to connect natively to any ASI or PCIe I/O subsystem eliminating the need for a separate bridging device, thus preserving system real-estate, power, and reducing cost on price sensitive I/O cards. By integrating PI-8 leaf bridging, developers can take advantage of the significant ecosystem of PCIe silicon while enhancing their platform’s capabilities with Advanced Switching’s features.
PCIe to ASI Root Bridge – Kestrel:
Kestrel is a PCI Express to Advanced Switching bridge designed to connect a wide variety of processors with PCIe root interfaces into an ASI fabric. PCIe will be the most prevalent bus interface used by next generation CPUs, NPUs, and DSPs. The Kestrel bridge and its associated software is processor agnostic and will provide full function bridging into an ASI fabric for PCIe capable Pentium, PowerPC, ARM, and MIPS processors. In order to interoperate with ASI-SIG defined standards-based fabric management software, Kestrel includes a fully compliant ASI portal. The bridge also enables multiple native ASI data movement protocols and PCIe tunneling (PI-8) compatibility.