ClariPhy Cleans Up 10-Gig
ClariPhy makes clock and data recovery (CDR) chips that go inside tunable DWDM transceiver modules. The chips perform digital signal processing to clean up high-speed signals, overcoming dispersion effects.
The 45-employee startup has been around since 2002 and originally wanted to do its work in enterprise networks, targeting 10-Gbit/s Ethernet links for what's now the Institute of Electrical and Electronics Engineers Inc. (IEEE) 802.3aq standard, also called 10GBase-LRM. (See ClariPhy Targets 10 Gbit/s.)
In 2007, ClariPhy decided to include telecom in its scope as well, showing off its technology at ECOC. (See ClariPhy Visits ECOC.)
And as it turns out, its first shipping product will be for telecom -- the CL1012 chip for 300-pin, 10-Gbit/s transponders.
ClariPhy is set to announce the chip just before OFC/NFOEC later this month. The chip has been sampling for about six months and should be ready for volume production during the second quarter of this year, CEO Paul Voois says.
ClariPhy's chips perform electronic dispersion compensation (EDC), picking out the zeroes and ones from a potentially distorted signal.
The method ClariPhy uses is maximum likelihood sequence detection (MLSD), a technique commonly used in storage systems and cellphones but usually considered too expensive or power-hungry for high-speed systems.
Plenty of competition exists for EDC chips of all stripes, enterprise or telecom. Other chipmakers in the field include Applied Micro Circuits Corp. (Nasdaq: AMCC), Inphi Corp. , Phyworks Ltd. , and Vitesse Semiconductor Corp. (Nasdaq: VTSS). (See Phyworks Works It.)
But the most direct comparison with ClariPhy is subsystems company CoreOptics Inc. , which applies MLSE -- maximum likelihood sequence estimation -- to metro and long haul 10-Gbit/s transmissions. But it's doing so with multiple silicon germanium (SiGe) chips. (See CoreOptics Lands $25M, CoreOptics Pushes MLSE, and ADVA, CoreOptics Partner.)
ClariPhy has been working on a less expensive route, building its chips from complementary metal-oxide semiconductor (CMOS) processes. That would result in a cheaper, silicon-based chip that could be easily integrated into other chips.
The lower expense is what ClariPhy is counting on. The company's chips will cost more and use more power than a typical CDR chip. ClariPhy thinks it can get away with the extra power, given that MLSD will let carriers run 10 Gbit/s on a wider range of old optical networks. The price is going to have more weight in deciding how successful ClariPhy is, Voois thinks.
"With the CMOS, we feel we have the pricing flexibility where we can make some money and they can deploy it everywhere," Voois says.
ClariPhy got its Series B funding in August, an unannounced round that brings its funding total to $40 million.
That's enough to get ClariPhy's first products into volume production, but Voois says he'll probably have to go out for more funding in 2010. "I'm not looking forward to that, honestly," he says, noting he's worried less about whether ClariPhy can get money than what kind of valuation it will receive. "Venture capital for the chip industry is not pretty right now."
— Craig Matsumoto, West Coast Editor, Light Reading