Startup Spins Novel Network Processor
That pretty much sums up Cognigine Inc., a startup that today announced additional funding of $10.5 million (see Cognigine Gets Another $10 Million).
Cognigine (pronounced cog-ni-jine) is working on a full-duplex OC192 (10 Gbit/s) network processor, a chip that sits in switches and routers, reading the headers of incoming data packets to figure out how they should be handled.
The startup reckons it's hit on an architecture that will enable it to deliver the first widget of this sort to support OC192 line rates and operate at wire speed.
Of course, plenty of other developers of network procesors are claiming that they'll be able to achieve similar, or even substantially higher speeds sooner or later (see, for instance, Swedes Claim Processor Advance). But all of them, including Cogingine, have yet to ship their chips and prove that they can actually deliver on their promises.
In Cognigine's case, the company hopes to announce product details in December and start shipments early next year, if everything goes according to plan.
Cogningigne claims big savings in real estate by offering full packet processing functionality on a single chip. In contrast, many network processor vendors today are opting for multichip solutions. They offload well-defined functions like packet classification and traffic management onto separate, hardwired chips, freeing up the power of the network processor to do the more complicated tasks.
This isn't the right way to go, because it sacrifices programmability, asserts Nick Kucharewski, the startup's president and CEO. And, of course, it requires more board space.
In addition, Conganignie's claiming that it can process packets in fewer clock cycles than other types of network processor. That's an important factor in achieving wire-speed performance, says Kucharewski.
How is this done? According to Kucharewski, the key is a "distributed microprocessor architecture". The network processor chip is composed of multiple processor cores -- 16, in fact -- connected by a switch fabric. Rather than have each processor core processing a single packet from start to finish, a single task is handled by several processor cores simultaneously. It's possible to do this by dividing up each task into more basic operations.
What's more, Congnognagong's come up with a way of allowing one processor core to handle more than one operation at once. It does this by allowing operations on small pieces of data (8, 16, or 32 bits) to be concatenated to fill the 64-bit-wide data path. As a result, a single processor core can do up to eight operations per clock cycle.
The architecture was invented by company CTO Rupan Roy, who used to develop graphic accelerator chips (which also use parallel processing technology) at Chips & Technologies, a company bought by Intel Corp. (Nasdaq: INTC) -- giving Cogmenahamenahamena something in common with ClearSpeed Technology Ltd.. Clearspeed also started out making graphic accelerator chips and then decided network processors were a better bet (see All Change at Clearspeed ).
However, the architecture is not without its downside. The instruction set that controls the way operations are shared out among the processor cores is very complicated. To hide this complexity from the user, the company added another level to the architecture, translating from one level to the other via an on-chip "dictionary" lookup.
That will make the chip harder to debug, reckons Steve Bassett, senior manager for network processors at Vitesse Semiconductor Corp. (Nasdaq: VTSS).
Bill Klein, network processor product manager at Agere Systems (NYSE: AGR), thinks the complexity of the underlying instruction set could be the product's undoing. "It looks impressive, but putting down multiple engines and trying to schedule them is a very difficult thing," he says.
Even if the new chip performs, it's going to have its work cut out for it, competing against the internal ASIC development groups of system vendors, as well as regular chip makers like Agere and Vitesse.
Cognigine's venture capital funding came from Draper Fisher Jurvetson, Lucent Venture Partners Inc., Wasserstein Ventures, and others. The $10.5 million total announced in today's press release includes $2.5 million in lease financing from Costella Kirsch Inc.
— Pauline Rigby, Senior Editor, Light Reading