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Chip "Could Boost Metro Market"

Light Reading
News Analysis
Light Reading
1/29/2001

Today, startup Paxonet Communications Inc. (formerly Core El MicroSystems) announced its first silicon product -- a granular crossconnect chip for handling legacy traffic over Sonet (see Paxonet Offers Sonet/SDH Crossconnect).

Paxonet also named a customer for the chip -- Mayan Networks Inc., a multiservice provisioning platform (MSPP) vendor -- and says it will have a second customer announcement very soon.

The beauty of Paxonet's chip, the Viti-48, is that it can deal with units of legacy traffic (T1, E1 and so on) individually, down to half megabyte chunks. In other words, it can reach inside STS-1s -- the smallest unit of Sonet -- to link any virtual tributary (VT) at the input to any VT inside any of the STS-1s on the output, according to Chetan Sanghvi, Paxonet's founder and CEO.

This will be a real boon for manufacturers of metro gear, who need a way to integrate legacy traffic into the new network architecture with minimum fuss.

Paxonet packs a lot more functions into a single chip, according to Sanghvi. "Our customers are taking something that used to occupy an entire box and looking at putting it on one or two line cards," he says.

Though equipment vendors such as Cisco Systems Inc. (Nasdaq: CSCO) already incorporate chips with similar functionalities into their products, they've had to develop them in house. Paxonet's chip is one of the first to be offered off-the-shelf, which should help its customers speed up product development times considerably.

Sanghvi says that he knows of only one chip maker that offers anything comparable to his company's chip. PMC-Sierra Inc. (Nasdaq: PMCS) offers a cross connect called TUDX (see http://www.pmc-sierra.com/products/details/pm5365/. But PMC-Sierra's product has an aggregate capacity of 312 Mbit/s. So in theory it would take 64 of them to equal the capacity of the Viti-48 (2.5 Gbit/s), he says. "I say in theory because it's not practical to link so many devices," he adds. (PMC-Sierra could not be reached for comment.)

The Viti-48, on the other hand, can be scaled to reach OC-192 (10 Gbit/s) levels, which requires 16 chips in a parallel architecture. A Clos architecture would use slightly fewer chips (12), Sanghvi notes. But, the benefit of Paxonet's approach is that no logic "glue" is required between the chips in order to scale them, he adds.

Production volumes of the Viti-48 should be available from March 2001.

— Pauline Rigby, senior editor, Light Reading, http://www.lightreading.com

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