Agere Unveils SerDes Subcircuit

ALLENTOWN, Pa. -- Agere Systems (NYSE: AGR.A, AGR.B), the world leader in communications components, today announced a Synchronous Optical Network (SONET)-compliant Serializer/Deserializer (SerDes) sub-circuit that reduces power consumption of chip technology by approximately 70 percent and halves the number of silicon devices required per channel on a circuit board. These improvements enable an increase in overall system channel processing capacity by a factor of four or more compared with competing silicon offerings. By integrating this SerDes into an Application Specific Integrated Circuit (ASIC), equipment manufacturers can directly connect Agere's ASICs to Agere's Netlight(r) optoelectronic transceivers. For targeted line card applications, this system architecture adheres to the SONET 2.5 Gigabits per second (Gbits/s) Optical Carrier (OC)-48 standard. SONET OC-48 is a widely deployed communications transmission protocol for connecting voice, data, and video signal transmissions. By integrating Agere's SerDes TSDR04 sub-circuit (macrocell) into Agere's ASIC chip, customers do not have to use a separate SerDes multiplexer/demultiplexer (mux/demux) chip or chips, as is the case with competing offerings. This integration lowers silicon costs and reduces the area used per port (per channel) in the same size system, thereby allowing an increase in SONET channel processing capacity on the same line card. By integrating the SONET-compliant TSDR04 SerDes macrocell onto the ASIC chip, Agere reduces the price per channel on a telecom line card by approximately $50 to $100. The TSDR04 chip technology also consumes 200 milliwatts per channel, approximately 70 percent less than competing SONET compliant silicon offerings. By integrating a single four-channel TSDR04 Serdes into an ASIC, customers eliminate four separate mux/demux devices from a four-port system, thus saving circuit board space and reducing cost. Agere Systems