Zarlink Intros Digital Timing Chip

OTTAWA -- Zarlink Semiconductor (NYSE/TSX:ZL) today launched a fully featured, high-speed digital timing chip that allows access and metro equipment designers to quickly and cost-effectively meet SONET/SDH (Synchronous Optical Network/Synchronous Digital Hierarchy) network synchronization requirements. To avoid network errors, SONET/SDH standards stipulate that all system elements, including a diverse range of access and metro equipment, comply with stringent specifications for network timing and synchronization. As a result, SONET/SDH equipment must be equipped with timing circuitry capable of generating carefully controlled output clocks. Zarlink's ZL30407TM digital PLL (phase locked loop) chip delivers an extensive set of output clocks and reliability features that simplify, shrink, and lower the cost of standards-compliant timing circuits for access and metro equipment. The device complies fully with Telcordia's GR-1244 and GR-253 standards for SONET minimum and Stratum 3 clocks, and the ITU's (International Telecommunication Union-Telecommunications) G.813 Option 1 and 2 for SDH clocks. In holdover mode, the ZL30407 meets the exacting demands of Stratum 3E and G.812. "We're saving designers time, money, and board space by driving complexity out of timing circuitry," said Michael Rupert, marketing manager, Timing and Synchronization, Zarlink Semiconductor. "Timing circuits based on our chip are easier to build than in-house designs and help designers achieve faster time-to-market." Zarlink Semiconductor Inc.