TriCN to Preview SerDes 'Engine'

SAN FRANCISCO -- TriCN, a leading developer of intellectual property (IP) for high-speed interface technology, today announced the introduction of its groundbreaking Serializer/Deserializer [SerDes] technology, named TriDL G2 (Digital Dynamic Deskewing Link). TriDL G2 is an ultra high-performance I/O interface “engine” that is capable of delivering up to 5 Gigabit/second throughput with significantly lower power and area requirements than comparable analog solutions. The TriDL G2 SerDes will serve as the core, underlying technology for TriCN’s upcoming introduction of PCI Express and XAUI interface products. “TriDL’s all-digital implementation is a dramatic departure from the competition,” explains Ron Nikel, Chief Technology Officer with TriCN. “The all-digital approach not only provides savings in area and power usage, but also streamlines porting and testability, and offers increased noise immunity not found in analog based devices. This is a powerful and unique combination of features that will be extremely attractive to designers of high performance semiconductors used in communications, networking, data storage and memory markets.” The TriDL G2 architecture consists of a transmitter hard macro, and a receiver hard macro. The modular design of the TriDL G2 SerDes allows semiconductor developers to integrate the TriDL G2 SerDes IP in bundles of 1 to 32 lanes, yielding as much as 320 Gb/s aggregate data rates, sufficient to meet even the most aggressive throughput requirements. TriCN Inc.