Net Processors Aim for Access
SAN JOSE, Calif. -- As demonstrated by announcements at this week's Network Processors Conference show, high-end network processor manufacturers are moving toward lower-priced chips targeted at the access and edge markets.
Announcements from EZchip Technologies and Applied Micro Circuits Corp. (AMCC) (Nasdaq: AMCC) today showed how both companies are taking advantage of semiconductor technology to improve network processors, but the increased power appears most likely to target systems designed for the edge of telecom networks, rather than the core. Separately, startup Azanda Network Devices is daring to push even closer to the edge, with a traffic management chip aimed at OC12 line speeds.
Special attention is being placed on the edge and access markets, and even enterprise markets, because that's where money is being spent. What's interesting is that even those that appeared to be developing chips geared for the core of telecom networks are able to morph themselves into access players.
Take the case of EZchip, which burst on the scene in 1999 bragging of a super processor to handle all 10-Gbit/s requirements in a single device. The company this week announced a faster, more powerful version of that chip, but officials also stressed that their products are finding uses in lower-end systems.
The new NP-1c is an enhanced version of the NP-1 network processor, which began shipping last spring (see EZchip Sallies Fourth). The NP-1c takes advantage of improved semiconductor technology -- transistors with line widths of 0.11 micron, rather than 0.18 micron for the NP-1. This helps increase the clock speed and add more processing elements on chip. The NP-1 funnels packets through a pipeline of these processors -- like a car going through a car wash -- so that more processors are required in order to keep up with faster line speeds.
In all, the NP-1c uses 30 percent less space than the NP-1 and boasts twice as much processing power, chief executive Eli Fruchter says.
The suitability for lower-end boxes comes in when you consider the price. The NP-1c sells for $795 and the original NP-1 for $1,175. This is lower than EZchip had first hoped, but the company had to make that tradeoff as the core-router market degenerated, Fruchter said. Moreover, EZchip adds features such as classification and table lookups without the use of additional chips such as external CAMs or SRAMs, further lowering the cost of the resulting line card, Fruchter says:
"We see ourselves today going into Layer 2 switches. We are getting into boxes that would not be using network processors if it were not for the price."
AMCC, meanwhile, is preparing its next wave of network processors with a 5-Gbit/s full-duplex chip (that is, it can process 5 Gbit/s of ingress traffic and another 5 Gbit/s of egress traffic simultaneously). The chip targets edge-minded systems such as DSLAMs as well as metro switches.
The new chip includes the traffic-management hardware that AMCC sells in its nP5700, a chip that sits between the network processor and the switch fabric. Line cards sometimes use a hardware-based traffic manager to juggle the multitude of traffic streams heading for the switch fabric (see our recent research report, Traffic Manager Chips), and many companies -- EZchip included -- have discovered the need to offer a traffic manager alongside their network processor.
Previously, AMCC didn't merge the nP5700 with a network processor because the resulting chip would be too large and would probably be too expensive for access and edge markets. The availability of smaller semiconductor geometries -- line widths of 0.13 micron -- is making the integration feasible, says Keith Morris, director of product strategy.
AMCC is referring to the technology behind its new chips as nP5, although the actual product numbers will be of the form nP3xxx. In addition to integrating the traffic manager, AMCC is adding a buffer unit where packets await to be reassembled upon arrival. For line cards dealing with hundreds of channels per port, this kind of reassembly is often handled by an ASIC or FPGA that sits in front of the network processor, Morris says.
The most dramatic thrust towards the edge has to be Azanda's. Founded as a traffic-management specialist with aspirations of OC768 (see Azanda Network Devices), Azanda scaled back its ambitions to the more realistic OC48 market earlier this year (see Azanda Flips Its Chips).
Subsequently, customers told Azanda about applications even further out from the core, in legacy OC12 networks. So Azanda is taking another step back to offer a chip, called Saber, targeting legacy OC12 networks.
"A lot of what you're doing in the access space is taking all these subscriber connections and aggregating them onto these Layer 2 VCs [virtual circuits]," says Greg Wolfson, Azanda's vice president of marketing, "and that takes a lot of shaping and scheduling."
The first Saber chip, the AZ61120-100, handles IP, ATM, and Frame Relay traffic simultaneously, and can sort traffic into four priority levels and eight service classes.
The NP-1c is slated to sample in the first quarter of 2003. AMCC expects to deliver the first of its nP5 chips in the second half of 2003. And Azanda's Saber is sampling now, with production shipments expected in the first quarter of 2003. — Craig Matsumoto, Senior Editor, Light Reading