SUNNYVALE, Calif. and SAN JOSE, Calif. -- Cortina Systems and Cisco Systems (NASDAQ:CSCO) today announced the Interlaken protocol specification: a new technology for high-speed chip-to-chip packet transfers. Jointly owned and developed by Cortina and Cisco, this new specification eliminates the cost and performance barriers of existing interconnect standards by taking advantage of serial technology to build much higher-performance networking equipment.

"Network equipment designs have hit a wall where chip-to-chip interfaces in the data plane are a gating factor limiting the density and overall bandwidth of network equipment," said Mark Gustlin, a technical leader in the Service Provider Routing Technology Group at Cisco Systems. "Interlaken allows use of the latest 6 Gbps serial technology in configurable increments, allowing designers to build interfaces that suit today's 20-40 Gbps applications as well as the 100+ Gbps systems of tomorrow. The efficiency of this approach effectively removes the interface as a barrier to higher-density silicon and systems."

Interlaken builds upon the logical structure of the prevalent SPI4.2, or System Packet Interface Level 4, technology now widely used in networking equipment. It preserves the capabilities of SPI-4.2 with multiple logical channels and back-pressure information, while eliminating its bandwidth ceiling and drastically curtailing its associated pin-count cost. With Interlaken's 90 percent chip-to-chip signal trace improvement, performance is increased while both board and chip design costs are reduced.

"Unlike previous interfaces, Interlaken works with any number of serial lanes, so designers can tailor the implementation to the specific bandwidth requirement," said Jim McKeon, product manager at Cortina Systems. "In addition, Interlaken uses a highly efficient encoding mechanism with much less overhead than XAUI's 8B/10B, while maintaining DC balance, transition density, and lane alignment."

Cortina Systems Inc.

Cisco Systems Inc. (Nasdaq: CSCO)