MOUNTAIN VIEW, Calif. -- Underscoring its commitment to deliver and support power-efficient solutions, Actel Corporation (Nasdaq: ACTL) has enhanced its Libero(TM) Integrated Design Environment (IDE) to further ease the system-level design process when using its field-programmable gate arrays (FPGAs). With SmartDesign, a new design entry capability that enables users to design at a higher level of abstraction, Actel's Libero IDE v8.0 significantly reduces FPGA design and development time, thus speeding customers' time to market. The enhanced tool suite supports all the company's FPGAs, including the flash-based, low-power ProASIC3 and 5 Micro Watt Actel IGLOO(TM) FPGAs, as well as the company's single-chip Actel Fusion(TM) Programmable System Chip (PSC), a mixed-signal power management FPGA.

A key functionality within Libero IDE v8.0, SmartDesign lets users visually create and then automatically abstract block-based system designs into synthesis-ready VHDL or Verilog components. The graphical block-based design entry supports prefabricated blocks from Actel's extensive DirectCore and SmartGen IP libraries. It also supports custom blocks created in HDL or Synplify(R) DSP and processor subsystems created with Actel's CoreConsole tool.

"Helping designers to stay within their ever-tightening power budgets, Libero excels with its accurate and easy-to-use SmartPower power analysis tools. The 8.0 enhancement to the Actel Libero tool suite represents our latest innovation aimed at easing the design and support of power-efficient applications," said Rich Brossart, vice president of product marketing at Actel. "Whether users are designing an ARM processor, a Fusion-based subsystem or a portable application using our low-power IGLOO devices, Libero IDE v8.0 with SmartDesign speeds the design process and provides 'correct by construction' confidence."

Actel Corp.