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Analog Bits Lowers SerDes Power

Analog Bits unveils industry's lowest-power 40nm high-bandwidth SerDes

February 8, 2011

1 Min Read

MOUNTAIN VIEW, Calif. -- Analog Bits, the Integrated Clocking and Interface IP leader, today announced the commercial availability of the industry's lowest power 40nm, high-speed Serializer/Deserializer IP. The break through macro is programmable to support multiple protocols and small enough to be used in embedded SOC's.

The Analog Bits 40nm SerDes supports more than 100 lanes, from 1 to 12.5 Gb per lane on single IC with a mere 5mw per gigabit per second per lane power consumption. It is currently in production in multiple applications and is validated in over 30 industry standard protocols including PCI Express, SATA, XAUI, XFI, SGMII and delivers the lowest chip-to-chip communications latency.

"The new 40nm SerDes is ideal for high speed processors and consumer electronics devices in high definition TVs, set top boxes and game consoles. The IP's programmable features allow designers to use licensable IP to create highly differentiated SOC products while reducing design risk and speeding time-to-market," explains Mahesh Tirupattur, Executive Vice President, Analog Bits.

Analog Bits

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