PMC-Sierra Touts Flexible 10-Gig Chip

Networking chip is designed to meld networks by supporting a number of 10-gigabit Ethernet formats

May 1, 2001

4 Min Read
PMC-Sierra Touts Flexible 10-Gig Chip

PMC-Sierra Inc. (Nasdaq: PMCS) announced its latest family of framer chips for 10-Gbit/s Ethernet last night (see PMC-Sierra Unveils 10-Gig Widget).

The significant thing about these chips is that they support a variety of 10-Gbit/s standards prevalent on both local and wide-area networks, including Ethernet, ATM, and Sonet. That's a must for vendors of multiprotocol networking boxes that sit at the edge of the enterprise networks, directing traffic out into the long-haul carrier networks.

"We believe our customers will want to build single line-cards that interface to both the LAN and WAN," says Steve Perna, VP and general manager of PMC-Sierra's optical networking division.

Multiprotocol chips also offer vendors a way of sidestepping the problem of not knowing how telecom networks are going to evolve -- whether Ethernet will invade, whether Sonet will survive, whether there's still some life in ATM. Vendors can use such flexible chips to make gear that can be adapted for any of these environments.

Essentially, line cards built with the chips would become multifunctional, explains Perna. That means that if the customer wants to change from a 10-Gbit/s Ethernet WAN mode to an OC192c packet-over-Sonet (POS) mode, all he needs to do is flick a software switch. There's no need to bring in installers to physically change cards.

With all this in mind, PMC's XENON chipset handles no less than seven ways of transmitting data at 10 Gbit/s. The chips sit on a line card and interface between an optical module and a POS PHY Level 4 bus, a standard connection designed to handle packet, cell, and frame data at 10 Gbit/s (see PMC-Sierra Announces 10-Gig Interface).

In all, there are four chips in the XENON family, which support different combinations of those seven protocols.

The flagship member of the product suite, euphoniously called PM5390 S/UNI-9953, supports six of the seven modes, which are:

  • single channel OC192 (10 Gbit/s) packet over Sonet (POS)

  • single channel OC192 ATM

  • quad channel OC48 (2.5 Gbit/s) POS

  • quad channel OC48 ATM

  • 10-gigabit Ethernet LAN PHY -- a souped up version of gigabit Ethernet with ten times the data rate, and various bells and whistles in the form of extra traffic management features

  • 10-gigabit Ethernet WAN PHY -- this version of 10-gig Ethernet has been tweaked in a different way so that it can be sent across existing Sonet links at the slightly lower bit rate of 9.953 Gbit/s

    The seventh mode is supported on a separate, single chip, which handles 10 ports of gigabit Ethernet traffic.

    PMC-Sierra claims its chips score a number of firsts. It says it's the first vendor to release chips supporting the new high-speed bus. And that's as it should be, since PMC Sierra is the prime mover behind the Saturn development group, the consortium of chip makers and end users that defined the POS PHY Level 4 standard.

    More significantly, the company claims to be first to develop chips that support both the LAN and WAN versions of 10-gigabit Ethernet. Competing chip makers agree that this is an important development but one that doesn't surprise them.

    "It falls right along the lines of what's been discussed at the 10 Gigabit Ethernet Alliance," says Jeff Downs from the Ethernet group at Vitesse Semiconductor Corp. (Nasdaq: VTSS). "The roadmap for 10-gig Ethernet is pretty much in the open, so this is a target for many chip makers."

    Downs concurs that PMC's product announcement is a first as far as he's aware, but believes other vendors won't be far behind. "In the next three to six months you'll see more product announcements of this nature," he adds.

    He says that Vitesse will have some 10-gig Ethernet chips of its own soon, through its acquisition of Exbit Technology A/S (see Vitesse Buys Exbit).

    Ultimately, it is not clear if support for extensive numbers of protocols on the same chip will be the best way to go, Downs notes. "In a perfect world, these kinds of multiprotocol solutions are a nice way to go," he says. "But when it comes down to the implementation details, the question is, is it the most efficient way to do things? You have to make a tradeoff between cost, chip area, power consumption, and so on. Are vendors willing to pay the premium?"

    He also points out that PMC's announcement concentrates on single-channel inputs for 10-gigabit Ethernet and doesn't indicate support for a XAUI ("Zowie") type interface, which brings in a 10-Gbit/s signal on four wavelengths. This would prohibit the use of one of the optical module options laid down in the 10-gig Ethernet standard, which uses four-color coarse wavelength-division multiplexing (CWDM) (see IEEE Nails Down 10-Gig Ethernet Basics).

    -- Pauline Rigby, senior editor, Light Reading

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