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Neralink announces a family of semiconductor cores targeting metro Ethernet
September 23, 2003
LOD, Israel -- Neralink Networks, Ltd., a leading developer of Metro Ethernet networking technology, today announced the Metro Ethernet Intellectual Property Program, an effort designed to remove the cost and resource barriers for components vendors seeking to introduce new functionalities and technology for the Metro and Last Mile Ethernet Market, and equipment vendors seeking to reduce their Metro Ethernet solution costs and obtain new metro Ethernet technology. The Neralink Metro Ethernet Intellectual Property (NEIP) arms Metro Ethernet equipment and components vendors with a comprehensive offering of IP cores in Verilog / VHDL source code, test bench, test plan, software, firmware, and system functionality to enable reducing their costs and introduce new functionality and products. Neralink VHDL / Verilog FPGA/ASIC cores include Telecom Ethernet Switch Engine (TESE) at 24Gbps, traffic manager and scheduler with up to 256 queues, 1024 connection AAL5 SAR for 1Gbps, SPI-4, and in process to release Metro Ethernet Forum (MEF) Traffic Engineering compliance policer. Neralink guides participants in the program throughout the development process, with system specifications, design guides up to full turnkey projects. Neralink Telecom Ethernet Switch Engine (TESE) includes wire speed 24Gbps switching for more than 100 virtual ports, HW MAC learning and aging per Customer/VLAN/Port, VLAN and network TAG editing such as Qtag, Q-in-Q, MPLS and VLAN stacking. The Traffic manager and scheduler supports up to 256 queues with RED/WRED and can be adapted to support more queues. MEF compliance Policer supports up to 2000 VLAN/MPLS streams and for each can configure the right parameters according to RFC 2698. Neralink Networks
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