Rambus SerDes Hits 10-Gig
High-speed SerDes chips (or chip components, in the case of Rambus) are targeted at allowing systems vendors to use existing serial backplane links rather than having to switch to parallel-optical links. More than a dozen chip vendors are developing high-speed backplane SerDes chips, and several of them have gathered together as the High Speed Backplane Initiative (HSBI) to standardize their efforts (see Backplane Bandits Get Together).
To be clear, the chip doesn't transmit at 10 Gbit/s; it reaches 5 Gbit/s but doubles the number of total bits sent, using a trick called multilevel signaling.
Rambus's new offering is called RaSer X, pronounced "Racer X" (but not to be confused with the band or the cartoon character). RaSer X was announced at the Chip2Chip Conference, held this week in San Jose, Calif. (see Rambus Intros 10-Gig Serial Link).
True to Rambus form, the product is not a chip in itself, but a semiconductor "cell," or core, meant to be inserted into a larger chip.
Competitors disagree on whether the market is ready for 10-Gbit/s SerDes, however, as systems requiring that kind of speed might not hit the market for several years. "Right now, even if I had it, there wouldn't be any customers," says Jim Tavacoli, vice president of marketing and business development at Accelerant Networks Inc.
But Rambus officials say they're hearing interest in 10 Gbit/s. While lots of buzz is brewing around 3.125-Gbit/s SerDes -- used in the standard XAUI interface for 10-Gbit/s Ethernet -- Rambus officials say some developers want to jump straight to 10 Gbit/s, targeting designs that will hit the market in 18 to 24 months. "A lot of people want to go from 2.5 Gbit/s to 10 Gbit/s," says Pulin Desai, manager of network-product marketing at Rambus.
Rambus is hitting 10 Gbit/s by using a multilevel version of a signaling technique called pulse amplitude modulation -- PAM4 or 4PAM for short, depending on whom you ask. Under PAM4, the chip sends signals at a speed of 5 Gbit/s but sends two bits per pulse -- i.e., rather than a zero or a one, it sends 00, 01, 10, or 11 in a single pulse, doubling the total throughput of bits. Accelerant uses the same technique in its 6.25-Gbit/s SerDes.
Only a few companies claim they can currently hit 10-Gbit/s speeds with regular binary transmissions, where the favored format is non-return-to-zero (NRZ) signaling, also known as PAM2. Broadcom Corp. (Nasdaq: BRCM) announced its X-PHY family in March (see Broadcom Releases Transceivers) and has begun volume shipments. BitBlitz Communications Inc. announced its BBRX102 SerDes last month (see BitBlitz Intros 10G Transceivers) and expects to begin volume production in the first quarter of 2003.
Those competitors say multilevel signaling has its place but hasn't seen wide acceptance yet. "Because of the circuitry to decipher multilevel signaling, you would incur bigger die size and higher power on a given gigabit," says Leo Wong, vice president of marketing for BitBlitz. "You'd find NRZ is a much more straightforward way to transmit bits across a medium."
Still, PAM4 comes in handy for older backplanes where crosstalk can interfere with signals. For that reason, RaSer X can apply PAM4 signaling to particular traces. "Even on the same backplane, some traces you're running may be able to run at 2PAM, some you're running may be able to run at 4PAM," says Desai.
RaSer X also borrows some technologies from the predecessor RaSer V (see Rambus Unveils 6.4-Gbit/s Cell, such as the ability to tinker with equalization coefficients, allowing developers to compensate for signal loss.
Few companies are offering a high-speed SerDes as a core, but officials at Rambus say that at high speeds, it stops making sense to sell the SerDes as a separate chip, "primarily because of power," says Kevin Donnelly, vice president of Rambus's network connections division. "You can't afford to have all those discrete components."
Moreover, Rambus expects many systems vendors to continue spinning their own ASICs, in which case they're likely to integrate a SerDes core into their chip rather than buy a separate chip set, Donnelly says.
BitBlitz officials counter by saying cores would be problematic, given the variety of protocols and speeds possible on a line card. "You would have to integrate a core with every different component [possible] on the line card," says BitBlitz's Wong. "In high-volume applications, I might agree there would be cases when a core would make more sense." But even then, the cost of integrating a core into an ASIC probably well exceeds the $60 that BitBlitz charges for its quad 3.125-Gbit/s SerDes, Wong says. "I can see them minimizing [the cost], but I don't see how one could eliminate the need for at least one or two engineers to do the interface."
A lower-cost chip might be nice but still doesn't excuse a designer from power requirements, Rambus's Desai says:
"There are two big issues -- the cost of an actual transceiver chip and the cost of actual power consumption, because extra chips are going to consume power. Everyone's saying they want to integrate because power consumption is a cost they can't tolerate."
— Craig Matsumoto, Senior Editor, Light Reading