Mercury Ships RapidIO Silicon Core

Mercury Computer Systems, Inc. (NASDAQ: MRCY), announced today the availability of its serial RapidIO(R)-based silicon IP (intellectual property) core. The core is fully compliant with the Serial RapidIO Specification 1.2, designed for reuse, and optimized for performance, latency, and reliability in embedded communications and networking applications.

Mercury is co-developer of the RapidIO interconnect architecture, which is designed for compatibility with mainstream integrated communications processors, host processors, and networking digital signal processors. Serial RapidIO is the latest generation, scalable, reliable, low latency transport through switches and between devices that is critical to supporting the demands of embedded computing, wireless, and storage applications.

In 2004, Mercury announced a succession of products incorporating serial RapidIO technology: the implementation in the Mercury Ensemble development system; the multi-chassis functionality in the Mercury ImpactRT(TM) 3200 and PowerStream(R) 7000 systems; and a license agreement with a semiconductor company for the development and deployment of serial RapidIO IP in high-end switching solutions.

"The availability of robust silicon IP cores for RapidIO is an important step in the development of the RapidIO ecosystem," said Mark Skalabrin, vice president and general manager, OEM Solutions Group at Mercury. "The Mercury IP core is fully validated and production ready."

The Mercury IP core is a high-performance solution independent of physical layer (PHY) designs, implementation tools, and target technology. It can be implemented in endpoint and switching applications and is available for both ASIC and FPGA implementations. The Mercury IP core has a well-defined host interface to ease integration into a variety of host interface designs.

Mercury Computer Systems Inc.