IBM Claims 3D Chip Breakthrough
Today, most electronic chips comprise a single layer of transistors, which are connected to packaging or to other chips with an array of metal wires. But scientists the world over are trying to come up with a way of increasing the density and performance of electronic circuits by stacking layers of transistors on top of each other to make a "3D circuit."
IBM's technique for building 3D circuits involves patterning transistors on separate wafers, and then bonding completed wafers together using a low-temperature process. After bonding, the two circuits can be electrically connected by making holes in the upper wafer and filling them with metal, although this is yet to be demonstrated.
IBM's achievement is a bonding process that doesn't degrade the electrical properties of the transistors, says Kathryn Guarani, lead researcher for IBM's 3D IC program. Guarani has written a paper about it, to be presented at the International Electron Devices Meeting (IEDM) in San Francisco in December.
Others have tried -- with limited success -- to build 3D circuits sequentially, by fabricating one layer of transistors, depositing a new layer of material on top, fabricating transistors in the new layer, and so on, she says. Guarani likens this concept to baking a layer cake. "If the cake is baked each time a layer is added, it doesn't turn out well. The top layer will be fine. But the bottom layer, which has been baked many times, will be spoilt, and the filling will have melted." [Ed. note: Now she tells me!]
It's worth pointing out that Infineon Technologies AG (NYSE/Frankfurt: IFX) claimed to have achieved true 3D integration a few months ago, by soldering two chips together, and patterning the solder layer to create interconnections (see Infineon's Chip Sandwich).
There are subtle but important differences between IBM's and Infineon's developments, however. For a start, IBM can bond whole wafers, and then make batches of chips from them, while Infineon has to solder individual chips one at a time.
There's also a difference in scale. The connections in Infineon's chip are formed with bond pads and copper channels some 25 microns wide. IBM plans to create vias just a few microns in diameter. Vias are a standard way of connecting different layers of metallization on top of a "plain vanilla" IC.
Gurani contends that IBM's approach is one of true integration, whereas Infineon is starting from a packaging standpoint. "Packaging is getting so advanced that its starting to overlap with integration," she says.
The two developments also differ in their aims. Packaging people like those at Infineon are trying to shrink the length of the connections between different chips, to boost speed and simplify the wiring. What IBM is trying to do, says Guarani, is shrink the connections between the transistors within the same electronic circuit. "We want to do completely new chip designs that exploit the fact you can have transistors on multiple layers."
Such chips could be operate at much faster speeds. IBM's process also opens up the possibility of integrating different kinds of semiconductor materials, such as silicon for electronics and indium phosphide for optical devices, in a very close way -- although, again, this remains an idea that hasn't been proved in the lab.
— Pauline Rigby, Senior Editor, Light Reading