Fujitsu Micro Tackles 100G

LANGEN, Germany -- Fujitsu Microelectronics Europe (FME) announces the availability of its new ultrafast ADC IP based on the revolutionary CHArge-mode Interleaved Sampler technology (CHAIS) for use in its standard 65nm CMOS process technology. This new high-speed ADC technology provides breakthrough performance levels in a standard CMOS process, enabling the integration of multiple ADCs with tens of millions of gates of signal processing logic and memory on a single chip. Initially targeting use in coherent receivers for 100G optical transmission, the technology is also applicable to high-end test equipment and any other system requiring high-speed data conversion and processing.

The new CHAIS technology provides previously unachievable combinations of sampling rate, resolution and power consumption. These circuits avoid many of the limiting factors, such as restricted bandwidth and poor linearity, of conventional architectures to make ADCs with sampling rates of up to 100GSa/s feasible in CMOS for the first time.

Power consumption for the ADC is 2W typical per channel at 56GSa/s, which is unheard of for this performance level (ENOB>6) – a half-speed mode provides 28GSa/s at 1W per channel. A 1.75GHz input reference clock is internally multiplied to provide ADC sampling clocks with less than 100fs total rms jitter and less than 500fs I/Q ADC skew.

“With our new ADC technology in combination with the ability to integrate in excess of 50 million logic gates, we provide the enabling technology for upcoming telecom applications, such as 100G Ethernet and OTU-4”, said Dirk Weinsziehr, Vice President of Marketing and Development at FME. “Based on this technology our customers can build bespoke products with lower power consumption, higher integration and a unique manufacturability to secure their leading position in the market.”

Fujitsu Microelectronics Europe (FME)