Agilent Tests SerDes Core

BOEBLINGEN, Germany -- Agilent Technologies today announced that it has validated its third-generation SerDes core in a 90-nm CMOS process technology. Due to the core's superior noise immunity, modular design and low power consumption, storage and networking OEMs are now able to embed as many SerDes channels (each operating at up to 6.25 Gb/s) as needed onto a single ASIC chip.

"Our latest 90-nm validated SerDes core offers customers the flexibility to embed hundreds of SerDes channels on a single chip," said Kin Chan, director of engineering for the Networking Solutions Business Unit in Agilent's Semiconductor Products Group. "Agilent's unrivaled combination of high-performance IP cores, high-speed design and embedded test expertise is what maintains our position among the ASIC leaders."

In tests conducted at Agilent, the embedded SerDes ASIC achieved error-free transmission driving signals over FR4 material (at room termperature) a distance of 76 centimeters (30 inches) using two connectors. The 90-nm SerDes core is compliant with Ethernet XAUI and is designed to offer these industry-leading features:

* 1149.6 AC-Extest for testing AC-coupled connections between ICs onthe PCB
* LC-based oscillator for improved power-supply noise rejection
* Decision feedback equalization
* BERT on chip for channel optimization
* Automatic receiver DFE tuning
* Low bit error rate of <10-17
* Internal 100-ohm differential termination

Agilent's embedded SerDes ASIC development model provides support throughout the entire product life cycle. It incorporates testing capabilities as early as the definition of system-level architecture and accounts for in-circuit manufacturing test, functional test, system turn-on and debug, and field diagnostics. With this model, Agilent enables equipment manufacturers to develop high-bandwidth networking and storage systems with superior reliability and reduced size, complexity and cost.

Agilent Technologies Inc.