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How Startups Can Win as Moore's Law Ends

Harry Quackenboss
6/30/2017
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A few years ago, before people started talking about the end of Moore's Law, a venture capitalist on a panel at an investor conference was decrying how expensive it was to fund chip startups. "We can afford about one chip startup a year," he said.

Another venture capitalist in the audience spoke up, saying that his firm couldn't even do that. "I didn't mean our firm," the panelist replied. As he swept his arm over the audience, he continued, "I meant all of us combined."

This was partly a result of chicken-and-egg circumstances. In order to convince investors to fund a chip startup, the founders needed to come up with a really big advantage over what the incumbent vendors' products would be in a couple of years that couldn't be easily equaled by them. This required designing big, complex chips that would be manufactured using the latest foundry process, resulting in everything being expensive, from the large design team personnel expense and the EDA software to the lithographic masks to mass-produce the chips to manufacturing the chips in small batches.

Not more than a couple of years later, many started worrying about the slowdown in Moore's Law, and what this was going to do to the tech industry. Many were predicting gloom, as if it were going to bring a kind of high-tech Ice Age.

But for all of the negative consequences, there are positive implications of the slowdown. In recent months, there have been several announcements about Ethernet switch chip products in the 10Gbit/s to 100Gbit/s Ethernet category to challenge the incumbents, including:

  • Barefoot Networks
  • Innovium
  • Cavium (Xpliant acquisition)
  • Centec (China)
  • Nephos (Mediatek spinout)

Why, in the face of the end of Moore's Law, is this happening?

For the last half-century, the entire semiconductor industry has been marching to the beat of a concept first proposed by Gordon Moore, co-founder of Intel.

What Gordon first proposed in 1965 was not exactly what people often say it is. It wasn’t about doubling the number of transistors on a single chip. The title of his original paper, published in Electronics, was titled "Cramming More Components onto Integrated Circuits." Further, over the next decade as the concepts from the paper were distilled into a simple statement, the time frame for doubling components wasn't so precise. What it predicted was that the number of components (transistors) would double every year or two.

In 2005, Gordon spoke on the 40th anniversary of Moore’s Law at an event at the Computer History Museum in Mountain View, Calif. What Gordon said then was that there were three areas of improvement. (1) The spacing between components would shrink (2) The defect density would improve, enabling economically producible chips based on the process yields to be larger and (3) Incremental improvement in the component placement and circuit routing would reduce the amount of wasted space on the chips. Eventually, Gordon explained, the routing optimization methods improved to the point where there wasn’t any wasted space. It was then that the doubling of the number of transistors on a single chip slowed down from every 12 months to 18-24 months.

From the 1970s through the 1980s up until about ten years ago, the chip and systems vendors have marched to this cadence.

Intel and other vendors evolved strategies to allow evolution to occur at Moore's Law rate, with new product introductions that kept up with Moore’s Law, but did so in steps that allowed systems vendor customers, and in turn their end customers, to absorb new chip designs and produce new systems with new features and performance at attractive prices.

On the chip design and manufacturing side of the industry, this involved massive investments, where each new generation required larger investments than the previous generation. This was a fact of life for the entire design and manufacturing supply chain, from companies that make the design and simulation software, the photolithographic machines that made the masks, the robotic handling equipment, the clean room-grade HVAC systems, the shock-absorbing mounting systems for the manufacturing equipment on the chip design and production arena and even the purity of the silicon ingots that were sliced into wafers. It has driven industry consolidation, forcing smaller chip companies to outsource manufacturing to an increasingly smaller set of chip manufacturers.

It impacted the companies that built systems around the chips that needed to come up with ways to recoup their engineering investments before the next generation of chips forced them to redesign. It also impacted systems users. Business PC and server buyers started depreciating their purchases over two to four years. Many vendors of larger systems built their business models, and made investments in engineering around the principle of major new systems designs about every four years (a 4X change in Moore's Law).

If that is all in the past, where is the upside in Moore's Law slowing down? It starts with economics:

Chip designs: New chip designs won't become obsolete as fast. The systems that those chips go into will have longer useful lives.

Electronic design automations tools: The EDA tools that are tied to specific chip manufacturing processes will be useful longer. This means the EDA software vendors can invest in improvements that will reduce the investment and time to design new chips. It may even foster a new generation of EDA companies.

Chip manufacturing tooling: The cost of generating the photolithographic masks should come down, because the mask production machines will have longer useful lives.

Chip manufacturing equipment: Equipment used to print circuit designs, clean the in-process wafers and the robot arms that transfer wafers from one step to the next won't become as obsolete as quickly. With slower obsolescence, the fixed capital equipment can be spread out over more production, lowering chip manufacturing cost. Chip designers can afford to spend more time on creating and refining new architectural approaches. For smaller chip vendors, this may reduce the economies of scale advantage that the largest companies they compete with have.

With longer lives and lower cost per chip, new designs can be economically justified with smaller addressable markets. Instead of focusing on large chips that can do many things, specialized designs with a narrower range of capabilities will become economically feasible.

This is key to enabling chip startups again. But startups aren't going to have an easy time, because the same factors will make it attractive for large incumbent vendors such as Broadcom to produce variations within product families.

Although a lot of the implications of the slowdown of Moore's Law apply to the broader chip industry, there are some factors specific to networking, such as:

Network programmability
Although the introduction of OpenFlow and other software-defined networking technologies didn't trigger new simpler chip designs as some had predicted, several of the new designs feature programmability, both to facilitate inserting them into existing system designs with software written for Broadcom's features and SDK, and to support new control methods such as the P4 language.

Large available market
Data center, or more precisely, server networking, has become a very big part of the market with speeds increasing from 10 Gbit/s to 100 Gbit/s. The bigger the potential market, the more investment in R&D it will attract.

Narrower range of use cases
Over the last decade, the mid- to high-end of the market has addressed with switch chip designs with increasingly complex feature sets, including larger Layer 2 MAC and VLAN table sizes, complex TCAMs, support for a large number of ACLs and so on. Some of the clean sheet designs appear to be based on trading off, for example, fewer complex configuration options for perhaps more ports, faster on-chip data baths or bigger buffers. With the widespread adoption of BGP for server networking, this might be a large enough segment to justify a design just for this use case leaving out Layer 2 protocol support.

— Harry Quackenboss, Principal, Q Associates

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hquackenboss
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hquackenboss,
User Rank: Blogger
7/19/2017 | 6:16:15 PM
Re: A matter of perspective
T,

I aprreciate you reading my article.

I can understand that given the breadth of chips and systems, you can certainly findlots of examples where performance per pound, or value per dollar are improving every 18 months, but there are some big parts of the market where that isnt the case.  DRAM prices for the same performance aren't cheaper than they were 18 months ago.  Laptop prices are coming down significantly, but I think that has a lot more to do with shrinking demand than price/performance improvements.  The high-end 3lb 13" machines available a year ago are not much behind the comparable products today in terms of memory capacity, and processor speed, but the prices are lower.

But I share your optimism for continued improvements because of a subtle implication of Moore's Law (strict definition) slowing down.  It makes potential use cases that couldn't be justified based on, for instance, annual unit volumes, when a chip design was obsoleted by semiconductor process improvements every couple of years more attractive. And that's going to mean that systems customers will see benefits.
danjoe
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danjoe,
User Rank: Blogger
7/3/2017 | 7:10:40 AM
Identifying the ASIC/ASSP opportunities
Thanks for your great article Harry.

It raises a lot of interesting questions. I think there is a broad agreement that Moore's law is challenged. The very fact that Intel spent close to $17 billion for Altera is proof enough of that.

What interests me though is your assertion that this slowdown could make chip/ASIC/ASSP design more attractive again. It ties nicely with another trend that is emerging where the industry is now accepting that perhaps the COTS solutions that are out there are not a one-size-fits-all proposition. There is still a need for hardware acceleration of certain functions that could occur at the NIC, motherboard or at the CPU level. As I aluded to above, the Intel strategy is to use FPGAs for these acceleration features. This is the same strategy that Microsoft Azure has also adopted. Being a vendor of FPGA-based SmartNIC solutions, we would obviously support that point of view.

The question is where there is an opening for an ASIC/ASSP play going forward? The reason why FPGAs are ideal right now is that they can be reprogrammed and reconfigured quickly and easily to adapt to changing requirements. With the continued dynamism of the cloud/SDN/NFV market, then this would seem to be a very prudent approach. Once this settles down though and the requirements are stable and not expected to change much, then the ASIC/ASSP cost optimization path can make sense.

Another potential area that could make sense (as was also the case in the past) is basic "glue logic". A generic need to bridge, what could be a simple gap, but a necessary one, which shouldn't cost that much. With the move to COTS, the volume should definitely be there to justify this. Think crossbar switches back in the day. Not sexy, but great volume!

So what could the opportunities be? Where are the gaps that could be filled today?
t.bogataj
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t.bogataj,
User Rank: Light Sabre
7/3/2017 | 3:19:56 AM
A matter of perspective
The "slowing down" of Moore's law depends on whether you take it literally or in its generalised form. The latter ("The amount of [integrated] processing power you get for the same amount of money doubles every 18 months.") is still true and does not seem to be challenged.

T.
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