Zarlink Semiconductor introduces family of nine low- to mid-density TDM/TSI switches for converged and wireless networking equipment

February 17, 2004

2 Min Read

OTTAWA -- Zarlink Semiconductor (NYSE/TSX:ZL) ,the market leader in TDM switching, today launched a family of nine low- to mid-density TDM/TSI switches with the industry's widest range of programmable and integrated features, delivering performance advantages and driving down costs in wired and wireless network equipment.

Communications networks are evolving from a circuit-switched to packet switched infrastructure, allowing service providers to offer profitable new services and lower their operating costs. This evolution to a PSN (packet switched network) is expected to occur over several decades. Accordingly, designers require more flexible TDM switches optimized for use in networking equipment that must handle both packet- and circuit-switched services.

For example, IP-PBXs (Internet Protocol-private branch exchanges) that support enterprise VoIP (Voice over IP) services require TDM technology to interface with the circuit-switched PSTN (public switched telephone network). Similarly, TDM devices are needed in media gateways and wireless base stations for seamlessly transferring voice, data and multimedia traffic between legacy and emerging networks.

Zarlink has responded to customer requirements by completely updating its TDM/TSI non-blocking switching portfolio, recently introducing four high-density, eight medium-density, and today nine low-to mid-density TDM switches. The ZL50021 switching family includes the first commercially available 2 K and 4 K devices to integrate a Stratum 3 DPLL (digital phase-locked loop) in a monolithic integrated circuit.

"By combining switching with timing and other performance features, our low- and mid-density switches offer significant benefits for platforms delivering converged services," said Kam Aite, product line marketing manager, TDM/TSI Switching, Zarlink Semiconductor. "Integrated features such as per-channel A-Law/µ-Law translation, per-stream rate conversion and Bit Error Rate Test circuits, and a Stratum 3 DPLL with low intrinsic jitter, eliminate the need for external components, making designs simpler and less costly."

Zarlink Semiconductor Inc.

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