SAN JOSE, Calif. -- Xilinx Inc. (NASDAQ: XLNX) today announced the company is shipping the world's fastest design software for programmable logic and system design: version 5.1i of its Integrated Software Environment (ISE) software family. Starting now and continuing through the remainder of 2002, the company will introduce a series of embedded and system-level design tools that extend the ISE series solutions into the realm of system design. These products, along with EDA partner design tools and methodologies, optimize silicon performance with the company's flagship Virtex-II Pro Family Platform FPGAs.Xilinx is leveraging its proven market and technology leadership in logic design to stake out a leadership position in programmable system design, a rapidly growing market that's projected to more than double to nearly $6 B in 2004 from $2.6B in 2001, with FPGA and embedded design dominating the growth (Source: ARM, Dataquest, IDC, Xilinx estimates and company reports). As the fifth largest ASIC/PLD company worldwide with $1.02 B in revenues in FY2002, according to Dataquest, Xilinx commands 50 percent market segment share in the PLD industry-larger than all other competitors combined."Xilinx is making a significant contribution to the EDA tools industry. For example, IBM will be using future versions of these tools for its next generation ASICs including the Xilinx/IBM hybrid chip. And, with an installed base of more than 150,000 design seats, Xilinx EDA tools are widely regarded as part of the de facto standard methodology for programmable logic design," said Cary Snyder, noted industry expert at PC2 Consulting and former industry analyst at Micro Design Resources.ISE 5.1i delivers "ASIC-strength" tools to exploit Virtex-II Pro series silicon performance With ISE 5.1i, Xilinx is delivering "ASIC-strength" design tools to exploit the power of Virtex-II Pro silicon, ranging in device densities from 40,000 to more than eight million system gates. Designers will benefit from a 2X improvement in compile times (an increase from 100,000 to 200,000 gate/min) and a 40 percent gain in device speeds over last year's software release. In addition, they'll get early access to the most advanced device architectures for Xilinx FPGA products, such as Virtex-II Pro devices, several months before first silicon. ISE 5.1i allows logic designers to finish designs faster with less risk using key new features, such as: · True incremental design to enable more turns per day · Advanced Pinout and Area Constraints Editor (PACE) management tool to simplify the specification of device IO and pin assignment · Architecture wizards to simplify the design of the industry's most advanced multi-gigabit serial transceivers, and on-chip digital clock management capabilities · Macro Builder, to enable design reuse by capturing physical IP implementation and preserving placement informationAlready, Xilinx has announced the System Generator for DSP, which enables designers to model a DSP system and generate an FPGA implementation using The MathWorks Simulink and MATLAB tools. The company has also announced partnerships with Synplicity for physical synthesis, Wind River Systems for embedded design support, Monta Vista for embedded Linux support, Mentor Graphics for co-verification support, as well as leading EDA partner support for architectural synthesis tool joint development. Throughout the remainder of 2002, Xilinx will roll out a series of embedded and system-level ISE 5.1i family and EDA partner design tools that enable on-demand architectural synthesis and flexible hardware/software partitioning.In a separate release:Xilinx Inc. (NASDAQ: XLNX) today announced that next month the company will begin shipping the latest release of its popular ChipScope Pro tools, the most comprehensive set of on-chip debug and verification tools on the market today for designing programmable systems. An industry first, the ChipScope Pro version 5.1i includes IBM CoreConnect integrated bus analyzer (IBA) cores, core insertion tools, and an analyzer interface for on-chip capture of data related to on-chip peripheral bus transactions. The CoreConnect on-chip peripheral bus is the critical interface between the PowerPC processor and peripherals implemented with Xilinx Virtex-II series Platform FPGAs.Now, logic and system designers can monitor and view transactions and events that occur over the CoreConnect on-chip peripheral bus (OPB) using advanced triggering capabilities in ChipScope Pro. The new CoreConnect IBA core enables protocol error violation detection and reporting based on the IBM Developer's Standards for the CoreConnect bus. And, the analyzer interface allows the user to view the data in a bus cycle-level display complete with time stamps."The latest release of ChipScope Pro tool will define a new standard in real-time debug for both systems and logic designers," said Rich Sevcik, senior vice president of FPGA products at Xilinx. "We're providing unprecedented access and visibility to designers for on-chip debug and verification of critical bus interactions between the PowerPC and peripherals within Virtex-II Pro-based designs. With each release of our software, our goal is to put tools in the hands of designers that fully exploit the power of Virtex-II Pro FPGAs, helping them to overcome the challenges of embedded and system design."CoreConnect IBA Cores Enable Real-time Debug for Logic & System Design The new ChipScope Pro CoreConnect IBA core extends the popular logic analyzer core technology pioneered in ChipScope ILA (integrated logic analyzer) to system designs based upon the Xilinx' popular Virtex-II Pro platform FPGA devices. These transactions are captured in internal BlockRAM and accessed via a JTAG port, minimizing the number of debug pins required for system-level debug.ChipScope Pro 5.1i includes the Core Inserter flow, which enables designers to identify signals and nodes that exist in a design and to insert ChipScope Pro cores into the design netlist. The ChipScope Pro Inserter flow offers the flexibility to add and remove debug cores at any time throughout the design cycle. This new Core Inserter flow is in addition to the original core generation flow, which enabled designers to quickly and easily insert IBA bus analyzer and ILA logic analyzer cores into the HDL source for synthesis, implementation, and programming by way of the Xilinx ISE design software.ChipScope Pro 5.1i includes a completely redesigned analyzer interface developed for advanced system-level debug. The new project-centric interface allows users to interact and display data from multiple ChipScope Pro cores in separate data windows. Designers can now debug signals and busses using waveform, listing or DSP plot views, perform advanced trigger setup, and export data to either ASCII files, or VCD files for HDL simulator integration.Xilinx Inc.