At Metro Optical Networking Forum, Xilinx unveils strategy to penetrate MAN market, solve bottleneck issues; intros 10-Gbit/s NP core

July 25, 2002

5 Min Read

SANTA CLARA, Calif. -- At the Metro Optical Networking Forum today, Xilinx, Inc., (NASDAQ:XLNX) unveiled its strategy to increase its penetration in the $23 billion dollar metro area networking (MAN) market. Xilinx has determined, and industry observers agree, that increased demand for broadband services, virtual private networks and deployment of new services such as video on demand, will play a crucial role in a sustainable rebound of the current economic slump in the telecommunications sector. Xilinx' focus in the MAN market is designed to stimulate growth and address current "metro bottleneck" issues. Metro bottleneck issues arising from the disparity in bandwidth between the corporate LAN and the WAN continue to fuel product development in this space The challenge is that fiber optic rings circling major metropolitan areas were designed for voice traffic, and are now being used primarily for data traffic. Addressing this challenge requires the development and deployment of new equipment based on new and emerging standards, while simultaneously provisioning new services that demand advanced packet processing and traffic management technologies. "We believe that breaking through the MAN bottleneck will be key to leading the telecommunications industry out of its current slump," said Wim Roelandts, president and chief executive officer at Xilinx. "We have aligned ourselves with industry leaders and developed unparalleled solutions to provide the foundation for alleviating this bottleneck and spurring new growth across the industry."The combination of high performance and programmability make Xilinx solutions the ideal technology to bridge the gap between the LAN and WAN. Based on the industry's leading programmable FPGA architecture, the Virtex-II PRO supports an aggregated I/O bandwidth of up to 120 G/bs with core logic performance capable of supporting packet processing in excess of 100 million packets per second. The flexibility to accommodate design changes, even after deployment in the field, is key to catalyzing new MAN standards such as RPR and MEF as they continue to evolve. In a separate release:At the Metro Optical Networking Forum today, Xilinx, Inc. (NASDAQ:XLNX) announced that Allegro Networks, an innovative new edge networking supplier, utilized Xilinxâ Virtex-IIÔ Platform FPGAs in the development of the industry's first multi-router. Allegro's multi-router is a new class of internetworking device that supports the concurrent operation and processing of multiple logically and physically independent routers within a single system. In addition to its own internally-developed ASICs, Allegro Networks selected Xilinx programmable chips to maximize flexibility and time-to-market benefits. Allegro Networks is among a growing number of companies using Xilinx FPGAs to gain a competitive advantage. "We're building a system that has heretofore never been developed and set out on an aggressive schedule," said Dave Roth, engineering director at Allegro Networks. "We were confident in Xilinx's ability to meet their product road map commitments. As a result of our collaboration, we knew when selecting a certain device, a follow-on device would be there for future product development or enhancements."In a break from conventional router technology, Allegro Networks' multi-router system provides numerous physical routers and associated route processors within a single system. This allows carriers to lower capital and operational costs at the edge of their network, optimize router provisioning and service delivery times and generate new sources of recurring service revenue. The multi-router utilizes Xilinx Virtex-II FPGAs throughout the system. In a separate release:At the Metro Optical Networking Forum today, Xilinx, Inc., (NASDAQ: XLNX) and IP Semiconductors, unveiled the SPEEDRouter 10G (SR10G), the world's first full-duplex 10 Gb/s Network Processor core targeted for Xilinx Virtex-II FPGAs. Based on proven silicon from Xilinx and IP Semiconductors, the SPEEDRouter 10G eliminates the need to use Content Addressable Memories (CAMs) on 10 Gb/s line cards that consume up to three-fourths of the power in OC-192, Gigabit and 10 Gigabit Ethernet line card interfaces. This new solution is targeted at metro routers, 3G mobile IP aggregation routers, and data center switches and routers. "The SPEEDRouter 10G provides designers with a simple and highly flexible solution to address the issue of power-hungry CAMs in the data path," said Robert Bielby, senior director of Strategic Solutions at Xilinx. "The fully programmable platform enables Xilinx customers to build solutions in record time.""Xilinx FPGAs provided the ideal platform to develop our fully programmable SPEEDRouter 10G," said Dr. Jeppe Jessen, chief executive officer of IP Semiconductors. "Together with the fully programmable SPEEDAnalyzer lookup and classification ASSP from IP Semiconductors, router vendors will now have the flexibility and performance they need to design solutions for today's metro area networking applications."In a separate release:At the Metro Optical Networking Forum today, Xilinx, Inc. (NASDAQ: XLNX) and Bay Microsystems, a leading supplier of 10 Gigabit network processors, announced the successful completion of hardware interoperability testing between Xilinx Virtex-II Platform FPGAs and Montego, the flagship programmable packet processor device of Bay Microsystems' Internetworking Processor (InP) Family. As part of Bay's Internetworking Development System (IDS), the Xilinx Virtex-II FPGA is used to bridge two Montego devices to a Host CPU complex. The IDS significantly reduces development time required by designers of emerging communication systems ranging from 16 port 1GE up to OC192c by providing an integrated platform for hardware and software development. The companies also announced that Bay has joined the Xilinx Reference Design Alliance Program. "Real world OC192c/10G systems continue to push the limits of today's leading silicon and optical technologies," said Chuck Gershman, co-founder and senior vice president at Bay Microsystems. "Xilinx Virtex-II platform FPGAs with the flexible SelectI/O Ultra technology allowed us to optimize a flexible host and accountant interface to quickly bring a truly robust complete OC192c/10G application-ready system to market.""Our alliance with Bay Microsystems is a great example of how Xilinx Virtex-II FPGAs are providing seamless integration with a network processor for 10G systems design in the MAN market," said Sandeep Vij, vice president of Worldwide Marketing at Xilinx. Xilinx Inc.Allegro Networks Inc.Bay Microsystems Inc.IP Semiconductors A/S

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