Xilinx Reshapes FPGAs

It's the kind of shift that comes around only once every few years: Xilinx Inc. (Nasdaq: XLNX) is preparing field programmable gate arrays (FPGAs) that change the "shape" of chip circuitry and could make life a bit easier on chip designers.

Xilinx won't discuss product specifics until next year, but the company announced its application-specific modular block (ASMBL) architecture today (see Xilinx Touts New FPGA Architecture).

FPGAs are chameleon chips consisting of a grid of generic logic gates. By programming these gates, a designer can replicate any digital chip, provided the FPGA has enough space. For industries such as telecom, where chip designs can get big and complex, FPGAs provide a nice test vehicle. It's too expensive to manufacture the chip and then discover something's wrong, so the design gets implemented in an FPGA first, creating a bigger and slower version that can be debugged. Sometimes, an OEM will even use the FPGA version in a first-generation system, getting to market early while the "real" chip goes through manufacturing.

As FPGAs get bigger -- Xilinx is mulling a billion-gate chip, says Chuck Tralka, director of marketing -- they've created new problems for designers:

• All the input/output connections are on the outside of the chip, even though it's now possible to put them in the middle. So, the number of I/O ports grows as the chip grows. In some cases, this results in too much I/O, chewing up space that could have been used by a designer.
• In recent years, Xilinx and rival Altera Corp. (Nasdaq: ALTR) began offering "cores," prefab memory or microprocessor blocks that fit into the FPGA. This creates the jigsaw-puzzle problem of fitting those blocks in. Sometimes customers get bumped to the next largest chip because a particular block just won't fit right, Tralka says.

ASMBL will address these issues by packing I/O and cores into interchangeable columns spaced regularly across the chip like pinstripes. By packing programmed functions into columns and then changing the columns offered, Xilinx will be able to parcel out different ratios of memory, processing power, and I/Os, hopefully producing an FPGA that's closer to customer needs.

Xilinx plans to offer different ASMBL versions sporting different preset combinations of these columns. Still, even though the columns can be mixed in any combination, the company does not plan to build customized ASMBLs, a business that would take Xilinx away from its mass-production roots.

"I wouldn't say we have no interest [in customized parts], but at this point we're still focusing on building general-purpose devices," Tralka says.

The first ASMBL products should be announced in the first half of 2004, but Tralka wouldn't say when the chips will be available.

— Craig Matsumoto, Senior Editor, Light Reading