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Xilinx Reshapes FPGAs

It's the kind of shift that comes around only once every few years: Xilinx Inc. (Nasdaq: XLNX) is preparing field programmable gate arrays (FPGAs) that change the "shape" of chip circuitry and could make life a bit easier on chip designers.

Xilinx won't discuss product specifics until next year, but the company announced its application-specific modular block (ASMBL) architecture today (see Xilinx Touts New FPGA Architecture).

FPGAs are chameleon chips consisting of a grid of generic logic gates. By programming these gates, a designer can replicate any digital chip, provided the FPGA has enough space. For industries such as telecom, where chip designs can get big and complex, FPGAs provide a nice test vehicle. It's too expensive to manufacture the chip and then discover something's wrong, so the design gets implemented in an FPGA first, creating a bigger and slower version that can be debugged. Sometimes, an OEM will even use the FPGA version in a first-generation system, getting to market early while the "real" chip goes through manufacturing.

As FPGAs get bigger -- Xilinx is mulling a billion-gate chip, says Chuck Tralka, director of marketing -- they've created new problems for designers:
  • All the input/output connections are on the outside of the chip, even though it's now possible to put them in the middle. So, the number of I/O ports grows as the chip grows. In some cases, this results in too much I/O, chewing up space that could have been used by a designer.
  • In recent years, Xilinx and rival Altera Corp. (Nasdaq: ALTR) began offering "cores," prefab memory or microprocessor blocks that fit into the FPGA. This creates the jigsaw-puzzle problem of fitting those blocks in. Sometimes customers get bumped to the next largest chip because a particular block just won't fit right, Tralka says.


ASMBL will address these issues by packing I/O and cores into interchangeable columns spaced regularly across the chip like pinstripes. By packing programmed functions into columns and then changing the columns offered, Xilinx will be able to parcel out different ratios of memory, processing power, and I/Os, hopefully producing an FPGA that's closer to customer needs.

Xilinx plans to offer different ASMBL versions sporting different preset combinations of these columns. Still, even though the columns can be mixed in any combination, the company does not plan to build customized ASMBLs, a business that would take Xilinx away from its mass-production roots.

"I wouldn't say we have no interest [in customized parts], but at this point we're still focusing on building general-purpose devices," Tralka says.

The first ASMBL products should be announced in the first half of 2004, but Tralka wouldn't say when the chips will be available.

— Craig Matsumoto, Senior Editor, Light Reading

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techemail2003 12/4/2012 | 11:11:37 PM
re: Xilinx Reshapes FPGAs Xilinx still 1 1/2 years ahead. They have a pulse on the direciton of the technology.
chip_select 12/4/2012 | 11:11:34 PM
re: Xilinx Reshapes FPGAs Is that Xilinx is getting to the technology and more importantly the cost point where FPGAs could take over from ASICs that PMCS and their competitors produce, for moderately low volumes (less than 200k parts)

For example, Xilinx has a 1 million gate FPGA for $12. How can you compete with that?

And this new whiz-bang architecture, we'll see about those column options their offering, but the amazing thing is being able to connect to pins in the middle of the die. Hardly anyone does that now.

The successful model for a semi-conductor firm has gone from build your own fab to fab-less. Now I'm wondering if it's not going to a step farther to manufacture-less (fab-less-less, if you will), where chip companies put their IP and marking onto an FPGA, and sell those directly to OEMs.
chip_select 12/4/2012 | 11:11:33 PM
re: Xilinx Reshapes FPGAs I don't think it *is* irrational exuberance. In my experience the "gate" count that Xilinx puts out is pretty close to what the equivalent ASIC gates are, or pretty close. It's not the old divide by 4 factor it used to be.

And which part of the technology envelope do you believe ASIC/ASSP houses are having problems with? It's not core speed. That usually runs at 78/155 MHz. It's the I/Os, and just plain fighting with the technology to yield a part. If Xilinx wants to have that burden, great.

Flip chip has been around for a while, but for power pins. I have not seen anyone have signal pins used in the middle of the die. I believe that's what Xilinx has done.

And you want to talk about flavors? How about the fact that current ASIC vendors have to put all sorts of things into their products so they can sell to a wide variety of customers? That increases their die size/cost as well.

Look, I'm not an FPGA groupie. It's just that it's so hard to get a multi-million ASIC to yeild that if I can get around that, for about the same cost point, I'm going to do it.
mrcasual 12/4/2012 | 11:11:33 PM
re: Xilinx Reshapes FPGAs Not wanting to rain on Xilinx's parade, but I would hold off on the irrational exuberance about their 1M Gate FPGA for $12 displacing lots of custom silicon.

Anyone who deals with FPGAs knows that you need to take the gate numbers they quote with a LARGE grain of salt. That and the performance you get from an FPGA in terms of clock speeds will ALWAYS be less than an ASIC version. Always. Forever.

Now, that being the case, for low volume designs that don't push the edge of the technology envelope, FPGAs are becoming better options every day as they cram more and more stuff into them. The fact that the FPGA vendors can do a lot more volume across their many customers helps with the pricing as well.

It will be interesting to see how many variants of this Xilinx actually puts out. Each variant reduces their ability to amortize costs across multiple users but at the same time gives them broader coverage. A tough question to get 100% right.

Oh yeah, one final thing, I/O in the middle of the die is not a new thing. Flip chip I/O is common these days.
chip_select 12/4/2012 | 11:11:31 PM
re: Xilinx Reshapes FPGAs
Hmm...I definitely don't want to get into an argument here, but I'm having a little trouble coming to terms with what you've said:

"The last chips I worked on were all above 200MHz core speeds and they were considered "slow". They also had I/O that ran at >800Mbps. Lots of them"

together with

"somewhere on the order of 8, yes 8 I just checked the datasheet, of the biggest Virtex-2 Pro chips to implement if you looked at the gate and memory requirements and we yielded it just fine"

So, according to my calculations, it sounds like you've created a 15-20 million gate ASIC, with core speeds of +200MHz, with multiple I/Os running at +800MHz, that you had no problems yielding. This assumes that your design was mostly synchronous, and not largely combinatorial (would fit normally into an FPGA)

What the hell did you make? I'm assuming the I/Os to run at 800 MHz had were 622 MHz interfaces + FEC, and in order to satisfy the "lots of I/Os", it wasn't a 2.5 GB device. OTN-2 cross-connect, maybe? With SONET pointer processing?

Either way, if it's true, congratulations. That is quite an accomplishment. Maybe you could point me to a datasheet.
mrcasual 12/4/2012 | 11:11:31 PM
re: Xilinx Reshapes FPGAs And which part of the technology envelope do you believe ASIC/ASSP houses are having problems with? It's not core speed. That usually runs at 78/155 MHz. It's the I/Os, and just plain fighting with the technology to yield a part.

Flip chip has been around for a while, but for power pins. I have not seen anyone have signal pins used in the middle of the die. I believe that's what Xilinx has done.


There's no magic in getting ASICs or I/Os to work properly. Depending on what you are doing 78/155MHz may be just right or way too slow. The last chips I worked on were all above 200MHz core speeds and they were considered "slow". They also had I/O that ran at >800Mbps. Lots of them. For designs that are sub 200MHz core and of limited volume, I agree, FPGAs are definitely the way to go. Assuming you don't need something else special that the FPGA can't give you.

I know for a fact that others have done I/O in the middle of the die. This is definitely new to the FPGA domain, but not to the industry.

Look, I'm not an FPGA groupie. It's just that it's so hard to get a multi-million ASIC to yeild that if I can get around that, for about the same cost point, I'm going to do it.

As I said earlier, it's relatively easy to get big chips to yield if you do your job carefully. The last chip I worked on would have required somewhere on the order of 8, yes 8 I just checked the datasheet, of the biggest Virtex-2 Pro chips to implement if you looked at the gate and memory requirements and we yielded it just fine. Don't forget there's a big difference between unique, custom gates and tiled FPGA gates.

BTW, I'm not trying to bash FPGAs. I've been a big fan and user of them for a long time.

People just need to realize that they have their pros and cons. There will always be a requirement for custom ASICs and there will always be a requirment for FPGAs.

I've seen too many executroids buy into the Xilinx or Altera (got to keep things even) sales pitch without really understanding that the design they want can't be implemented in a single FPGA at the performance and feature levels they want.

It then gets left to the engineering team to try and sort it out and very rarely does that end well.
mrcasual 12/4/2012 | 11:11:30 PM
re: Xilinx Reshapes FPGAs So, according to my calculations, it sounds like you've created a 15-20 million gate ASIC, with core speeds of +200MHz, with multiple I/Os running at +800MHz, that you had no problems yielding. This assumes that your design was mostly synchronous, and not largely combinatorial (would fit normally into an FPGA)

What the hell did you make? I'm assuming the I/Os to run at 800 MHz had were 622 MHz interfaces + FEC, and in order to satisfy the "lots of I/Os", it wasn't a 2.5 GB device. OTN-2 cross-connect, maybe? With SONET pointer processing?

Either way, if it's true, congratulations. That is quite an accomplishment. Maybe you could point me to a datasheet.


Thank you. It was in fact quite an accomplishment by the team. Everyone who has seen the details has been suitably impressed. It worked on the first pass silicon too.

You were very close with your guess. The chip in question was approximately 15M gates (depending on how you count gates), had over 16Mbits of embeddeded memory, and over 50Gbps (full duplex) I/O bandwidth.

It wasn't a SONET chip. The interfaces were in fact 800Mbps unencoded data + clock. You generally only need FEC if you are sending data over long distances and have to maintain very low bit error rates in recovered clock environments.

Unfortunately, good execution and good technology does not always win the game, and the company that produced the chip is now out of business and the IP and assets are for sale.

The website is still up though. Gold star to the first person to identify the product.
talissomeone 12/4/2012 | 11:11:27 PM
re: Xilinx Reshapes FPGAs FPGAs will always be low end. The several devices I have worked on have all been larger than 3million gates and contained > 8Mbits of SRAM. The price point for these devices was around $14 to $20/piece and the core frequency was in the 500MHz+ range.

I agree, there is no secret to making ASICs function the first time. The same process is used to make ASICs as FPGAs.

Granted yield can be higher for FPGAs if they mask out by re-configurable areas. The devices I am working on know clock at 2GHz and contain a boat load of ram and need to be low power.

FPGAs are high power since the routing cannot be minimized.

My thoughts.
huaweisneighbor 12/4/2012 | 11:11:26 PM
re: Xilinx Reshapes FPGAs Can you SA people just put iPP RIP? Gee.
sigint 12/4/2012 | 11:11:25 PM
re: Xilinx Reshapes FPGAs talissomeone:
FPGAs will always be low end. The several devices I have worked on have all been larger than 3million gates and contained > 8Mbits of SRAM. The price point for these devices was around $14 to $20/piece and the core frequency was in the 500MHz+ range.
__________________________________________________
Well, low end is where the volumes are. RTL for very many standard functions can be no freely downloaded or cheaply developed - someone that is in the business of converting and IEEE standard to a box as cheaply as possible will find a cheaper FPGA solution. The added level of vertical integration means greater margin - and there you have a compelling story.

The fact that TSMC is running full capacity won't help in the short term either. Fab capacity has suffered during the downturn and could snowball into a seriously capacity issue over the medium term. Life saviours? FPGAs.

talissomeone:
FPGAs are high power since the routing cannot be minimized.
_________________________________________________
Design managers would often overlook indiscretions such as gated clock design if a 4 million dollar NRE isn't involved. :)

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