Ships IP cores for the Spartan-IIE FPGAs POS-PHY Level 3 and Gigabit Ethernet MAC cores for building OC48 networks

February 6, 2002

1 Min Read

SAN JOSE, Calif. -- Xilinx, Inc. (NASDAQ:XLNX - news), announced today the immediate availability of its POS-PHY Level 3 (PL3) and Gigabit Ethernet Media Access Controller (MAC) Intellectual Property (IP) cores for use with its Spartan-IIE FPGAs. The PL3 core is compliant with the Optical Internetworking Forum (OIF) System Packet Interface (SPI) --3 specification while the Gigabit Ethernet MAC (GMAC) core is compliant to the IEEE 802.3-200 standard. With these cores, highly functional, scalable and standards-based equipment supporting the OC-48 data rates can be easily built to meet the exploding growth of Internet traffic. "Ethernet is becoming a key technology driving the LAN/WAN convergence based on its broad industry acceptance and user familiarity," said Per Holmberg, senior product marketing manager for IP Solutions at Xilinx. "The combination of the cores and Spartan-IIE FPGAs provide system architects with the ability to quickly build cost effective and flexible solutions that can seamlessly connect newer Gigabit Ethernet systems to their existing SONET/SDH networks." Xilinx Inc.

Subscribe and receive the latest news from the industry.
Join 62,000+ members. Yes it's completely free.

You May Also Like