BURLINGTON, Mass. -- Xelerated, developer of the Xelerator(tm) X10q - the industry's only 40 Gb/s network processors, today announced two DRAM based search engines, the Xelerator(tm) LPSE-I and LPSE-II. Together with the Xelerator(tm) X10q-e network processor, these devices will enable system vendors to build high density line cards and service cards with large routing tables at one tenth the cost and power of CAM based solutions, and less than half the cost and power of other available DRAM based solutions.

As the number of unique routing prefixes grows in the global Internet, cost effective solutions that support large numbers of forwarding table entries are becoming critical for routing equipment. The Xelerator(tm) Longest Prefix Search Engine (LPSE) I and II are Mtrie search engines for IP forwarding table lookup, providing guaranteed deterministic search latency, and taking advantage of the latest developments in DRAM memory technologies.

"With the advent of high performance DRAM, it is no longer necessary to settle for inefficient network processor solutions that consume large amount of processing power in both the control and forwarding planes," says Gary Lidington, VP Marketing at Xelerated. "Using our LPSE-solution will enable network equipment OEMs to build robust IPv4/IPv6 forwarding solutions with 2 to 4 times fewer network processors, thus minimizing board space, power dissipation and cost."

The LPSE I and II use a unique combination of SRAM and RLDRAM-II to give optimum performance and price for forwarding applications of up to 2M entries, and for search rates of up to 90M search/s. Unlike previous network processor solutions that can consume as much as half the processing power of the network processor executing the search algorithm, the forwarding plane algorithm is implemented as a co-processor, freeing up critical processing resources for running the application. By using new, high performance standard memories, the LPSE is the first algorithmic search engine to provide enough bandwidth expansion to eliminate the need for complex table compression algorithms. This simplifies the table update process resulting in a more stable, higher-performance control plane, capable of withstanding the route flaps that can be generated by large networks. The two products differ in that the LPSE-I is optimized for IPv4 search only, and the LPSE-II provides table search operations for both IPv4 and IPv6.

"Xelerated has now taken the lead in the race to provide cost effective support of large forwarding tables," says, Bob Wheeler, Sr. Analyst at The Linley Group.

Together with the Xelerated X10q-e these search engines provide a 2 to 4 times reduction in power and cost relative to the nearest competitor. For example, a table look-up solution only requires one SRAM and four RLDRAM-II devices for a solution capable of over 1M prefixes for IPv6, and 1M prefixes for IPv4, or a total of 2M prefixes. In comparison with a TCAM based solution, which requires 6 TCAMs and 12 SRAMs, an LPSE solution with memory is more than a factor ten lower in cost.

In comparison with other network processor solutions, the high efficiency of the X10q's data flow architecture, coupled with the new LPSE-II search engine, makes it possible to build 40 Gb/s IPv6 solutions with over 1M routes, that dissipate less than 12 watts. That is less power than 10 Gb/s solutions using traditional, power hungry 10 Gb/s network processors which typically dissipate 12-25 Watts for the network processor alone.

Available in Q1 2004 the LPSE-I and LPSE-II will be provided as FPGA images for Xilinx Spartan-III devices which will be included with version 2 of the Xelerator(tm) Reference Design Kit and a control plane software package that will be included with version 1.4 of the Xelerator(tm) Software Development Kit.

Xelerated AB