Vitesse Chops Chips
Today Vitesse Semiconductor Corp. (Nasdaq: VTSS) unveiled a family of switch chips for building grooming switches -- ones that allow smaller pipes to be rearranged inside fat pipes so that network equipment can handle them more efficiently (see Vitesse Supports Good Grooming).
Called Timestream, the flagship member of the product family is a 160-Gbit/s switch chip capable of grooming STS1 (51.8 Mbit/s) circuits. It offers a fourfold improvement in density over Vitesse's previous grooming chip, which could only handle 40 Gbit/s.
The new chip brings Vitesse in line with competitors like PMC-Sierra Inc. (Nasdaq: PMCS) and Velio Communications Inc. (see Velio Breaks Grooming Barrier), which also offer 160-Gbit/s chips.
What's most significant -- and controversial -- about Vitesse's grooming chip is that it can be used to build bigger switch fabrics using half the number of chips as competing solutions, says Andrew Schmitt, product marketing manager for TDM products at Vitesse. Building a 640-Gbit/s fabric would require 24 of a competitor's chips, he contends, but only 12 chips from Vitesse.
The Timestream chip can do this because it uses a "strictly non-blocking" architecture, Schmitt claims. PMC-Sierra and Velio's chips, on the other hand, are "rearrangeably non-blocking", he says. (Honest! He said that: "rearrangeably...") In English, that means they're only non-blocking if used in the correct way.
"With strictly non-blocking, the outputs [on the chip] operate independently of each other. With 'rearrangeably' non-blocking," he clarifies, "the outputs need to be programmed together."
In the latter case, when a new configuration is loaded onto the chip, there is a period of uncertainty while the software works out how to adjust the outputs. It needs to retain the old configuration while that's going on, and that entails doubling up the working capacity of the fabric.
Being strictly non-blocking gives Vitesse's chip a couple of advantages, says Schmitt. First, as noted, it reduces the chip count when building larger switch fabrics. Second, since the software doesn't need to get involved when the switch is reconfigured, it's possible to do protection switching in hardware.
"In a Sonet ring there are two identical channels coming into the switch, and you need to pick the best one. With Vitesse's chip, this selection process is totally automated, and takes place in less than 1 millisecond."
When Light Reading contacted Vitesse's competitors to find out if its claims stood up to scrutiny, the whole issue immediately became a ball of hair. For starters, there are lots of qualifiers that need to be taken into account.
"Our switch is strictly non-blocking," says Bill Woodruff, Velio's VP of marketing. But when pressed, he admitted that Velio's chip is strictly non-blocking only for unicast applications. It's "rearrangeably" non-blocking for dualcast, and even has a very small chance of being blocking if used in multicast (broadcast) situations.
Woodruff goes on to say that he doubts Vitesse's claims. "I suggest their switch isn't non-blocking for dualcast, because it would violate the theorem of Charles Clos."
And I think we all know what that means. Vitesse insists, however, that its switch is strictly non-blocking for unicast, dualcast, multicast, plastercast, and any other kind of darned cast. "It doesn't violate Clos because the inside of our chip isn't based on a Clos architecture -- that's the point of avoiding the Time-Space-Time architecture our competitors use," said Schmitt, before being transmuted into another dimension.
Schmitt's not surprised by Velio's reaction, as he feels the non-blocking issue is generally quite poorly understood. "We sell a lot more of our TSI [time-slot interchange] fabrics to software guys than to hardware guys," he says. "They're the only ones who realise how difficult it is to work with these things.
"It isn't hocus-pocus architecture, because we do the same thing in the VSC9182, a 40G TSI [grooming switch fabric] that's in full production today."
But Velio has the last word. "Rearrangeably non-blocking is a red herring when it comes to building multistage Clos architectures," says Woodruff. "What's important is to ship products." And there he may have a point, as Vitesse's chip isn't due to start sampling until Q4 2001, while Velio says it's been shipping samples since March.
PMC-Sierra (which, ironically, does not begin with a "V") did not respond to requests for comments.
— Pauline Rigby, Senior Editor, Light Reading