Comms chips

TeraChip's Retro Switch Silicon

Startup TeraChip Inc. is emerging from stealth today with what it claims is the most compact switch fabric yet (see TeraChip Unveils 160-Gig Fabric). While that kind of announcment hits the wires every couple of months, TeraChip is unusual in that it's using an architecture that has been largely shunned by industry -- but it's also an architecture that tends to be cheap and efficient.

Based in Palo Alto, Calif., TeraChip raised $15.5 million in two funding rounds as of last April and has picked up another $3 million since (see TeraChip Raises $11M and Switch Fabric Startup Gets $4m).

Equally important, TeraChip has received chips from the fab, a key milestone at a time when customers are wary of big-talking startups. Company executives planned to ship initial samples to customers by early this week, and a public demonstration, with an as yet unspecified network processor partner, is slated for the Networld+Interop tradeshow in May.

Like most switch fabrics, TeraChip's TCF16X10 consists of two pieces: an interface chip that goes on every line card, and a switching element that resides on its own card.

But TeraChip uses what's called a shared-memory architecture. On paper, it's a simple and easy way to handle switching, but most companies abandoned this architecture because it's limited by the speed of the memory chips -- which weren't fast enough to handle the 10-Gbit/s line speeds most startups were shooting for.

"People published articles explaining why this is not a good path, but we implemented it," says Dror Sal'ee, TeraChip vice president of marketing.

In a shared-memory setup, data gets plopped into a common waiting area in memory, and output ports call up the appropriate packets when it's their turn to leave the switch. All line cards have access to the shared memory pool.

Contrast that with the crossbar architecture that's favored today, where data gets sent through a matrix of lines connecting all possible inputs and outputs. The switch matches its inputs and outputs by activating particular intersections within the crossbar.

"People are claiming this is getting tougher and tougher, because the switching speeds are running faster than the memory access," Sal'ee says.

Few other companies use shared memory for their latest switch fabrics. An exception is IBM Corp. (NYSE: IBM), but IBM requires that the central switching chips communicate along a bus, keeping them in sync, whereas TeraChip's architecture lets multiple switching chips operate independently, which helps them maintain their necessary high speeds, Sal'ee says.

TeraChip claims it's figured out ways to get commonly available memory chips to run fast enough to suit switching. Details are scarce, but it appears TeraChip connects to memory using an unusually wide bus -- one that can extract more bits per clock cycle.

The small number of chips used helps TeraChip save power. Moreover, because TeraChip doesn't use the multitude of queues associated with crossbar architectures, its chipset requires fewer backplane connections. "If you can save those pins and save those connections, you're saving a lot," says John Metz, principal analyst with Metz International Ltd.

All told, the central switching chip, the TCF16X10, consumes 15 W, putting it near the bottom in terms of power consumption (lower being good, of course).

TeraChip has also done well in terms of price -- about $800 for 160 Gbit/s of switching capability -- and overall performance, based on the numbers they've announced. "It's as good as anything else that's out there, regardless of what architecture they're using," Metz says.

— Craig Matsumoto, Senior Editor, Light Reading
fabric_man 12/5/2012 | 12:43:28 AM
re: TeraChip's Retro Switch Silicon I don't see much, if anything, about the interface chip (TCI1X2) in any of the press - only a short description of high-level functionality such as load-balancing and QoS.

This interface chip seems pretty important to the whole system. How about some more detail (including how it connects to the shared memory chip - TCF16X10) and also some pricing info?

- fabric_man
SiVlyGuy 12/5/2012 | 12:43:26 AM
re: TeraChip's Retro Switch Silicon $800 is a bargain for a 160G fabric. But I gather that this solution requires external memory. So that needs to be factored in to the price.
Dror Sal'ee 12/5/2012 | 12:43:25 AM
re: TeraChip's Retro Switch Silicon Guy,

You are right, it is a bargain.
The nice thing is, the solution requires NO external memory.

lovelypig 12/5/2012 | 12:43:23 AM
re: TeraChip's Retro Switch Silicon
As I saw from Tera-Chip.com, at least two planes are required for redundancy and speedup. Since there are memory inside each plane, I'm wondering what is their solution for cell/packet out of sequence problem?

If the delay between two planes can be bounded and not so large, the re-sequencing buffer in the egress TCI may solve the problem. What about if not? Furthermore, if 40Gbps are supported, more planes (say 8) may be required, then this out-of-sequence situation maybe aggravated. Or maybe they got some flow-level solutions.
fabric_man 12/5/2012 | 12:43:17 AM
re: TeraChip's Retro Switch Silicon > $800 is a bargain for a 160G fabric. But I
> gather that this solution requires external
> memory. So that needs to be factored in to the
> price.

You have to look carefully at the $800. That cost does not appear to include the line card interface device (TCI) - only the central shared-memory fabric. This interface device is doing a lot of work here - still no details on its function (or price) have been posted.

The line card device will most likely dominate cost anyway since there will be 16 of them in a 160 Gbps system as against only 1 (or 2 if redundant) shared-memory fabric device.

There are other companies out there with cheaper fabric devices (crossbar) that have 160 Gbps of capacity, even when 2x overspeed (required for crossbars) is factored in.

- fabric_man
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