Optical components

Swedes Claim Processor Advance

Swedish startup Xelerated Packet Devices AB is planning to unveil a novel network processor design at next week’s Supercomm 2001 trade show -- a design that could eventually scale to 160 Gbit/s, it claims.

Xelerated intends to achieve this feat with its "multi-stage programmable pipeline" architecture -- a way of reducing queuing of packets that speeds things up considerably.

The architecture also enables Xelerated's processor to handle different types of packets simultaneously. This makes it suitable for use in a wide range of equipment, including "service aware" switches that look deep inside packets to identify the characteristics of individual connections carrying different applications (see The Service-Aware Switch).

Network processors are still relatively new. They aim to help equipment manufacturers shorten development times by eliminating the need for them to develop their own ASICs (application-specific integrated circuits) to figure out how to switch packets.

Low-speed network processors are typically based on a single RISC processor that takes in a packet, processes it, and then forwards it before taking in another packet. This can take as long as 100 clock cycles per packet, according to Xelerated. The usual way of achieving higher speeds is to speed up the clock and have multiple RISC chips running in parallel.

Xelerated has taken a totally different approach with its network processor. It’s separated its work into as many as 20 discrete stages, each of which takes a single clock cycle to complete. This means that on every clock cycle, one packet goes into the chip and one packet goes out, assuming that the network processor is fully loaded. There are no yawning gaps waiting for packets to get processed.

In more detail: The first stage of Xelerated’s programmable pipeline “classifies” the packet under scrutiny. In other words, it figures out what type of protocol it is. If it’s, say, MPLS (multiprotocol label switching), it initiates an “MPLS program thread,” which tells subsequent stages how to deal with the packet. It’s then shunted into the second stage, allowing the first stage to start examining the next packet.

Other stages in the pipeline do things like calculating the checksum (to make sure the packet hasn’t been corrupted), changing the time-to-live setting (which prevents packets circulating forever), and figuring out what forwarding information should be sent to the switch.

As noted, the upshot is faster throughput. Xelerated is banking on using this concept to deliver the first commercial 40-Gbit/s network processors. It also figures it could achieve 160 Gbit/s by speeding up the clock in its chips. The startup has already proved the concept with simulations using software and field programmable gate arrays. It expects to ship first samples in the first half of next year.

One of Xelerated's competitors, who requested anonymity, isn't convinced that the Swedish startup's approach is so unusual and points to possible problems, noting that Israel's EZchip Technologies also uses a multistage pipeline approach. In EZchip's case, it has four stages, each using a different type of processor. One of the downsides of this approach is that each processor has to be programmed in a different way, making life complicated for customers.

The competitor also question whether Xelerated is implementing too much in hardware -- making it tough to program its network processor in different ways for different applications.

Xelerated was founded last August by Johan Hellqvist and Thomas Eklund, both of whom previously worked for Switchcore AB, a Swedish startup developing switching silicon (see Xelerated Packet Devices AB). Undisclosed funding has come from Startupfactory, a venture capital company owned by Investor, a large Swedish holding company, and Softbank.

— Peter Heywood, Founding Editor, Light Reading
http://www.lightreading.com For more information on Supercomm 2001, please visit the Light Reading Supercomm 2001 Preview Site.

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