Comms chips

Startup Claims Processor Breakthrough

What could prove to be a significant development in network processor technology is due to be announced on Monday (13 August) by Danish startup IP Semiconductors A/S.

The startup is claiming to have reached new highs in packet processing performance. It's set to unveil two chips: the SpeedRouter, which it claims is the industry's first full-duplex OC48 (2.5 Gbit/s) network processor, and a classification engine called the SpeedAnalyzer.

"We offer two- to five-times more processing power per packet, and a reduction in power consumption and device count by five," claims Jeppe Jessen, IP Semiconductors' VP of sales and marketing.

The additional processing capability can be leveraged to perform a "deep-read" of the packet, allowing carriers to offer advanced IP services and charge customers for them (see The Service-Aware Switch).

Bold claims. But do they stand up to scrutiny?

Applied Micro Circuits Corp. (AMCC) (Nasdaq: AMCC), which added network processors to its portfolio when it acquired MMC Networks, is quick to point out that IP Semiconductors isn't the only vendor with a full-duplex OC48 solution -- one that can process packets both going on and coming off the switch card. AMCC announced such a chip back in April 2001 (see AMCC Introduces Network Processors), and says it started shipping samples in June. IP Semiconductors also claims its chips are sampling now.

Other vendors, such as Agere Systems (NYSE: AGR), only offer uni-directional OC48 network processor chips, which means that they have to be doubled up on the line card. They also need row upon row of expensive memory chips to support them, according to Jessen.

Making direct comparisons between chips from different vendors is tricky, however. Jessen contends that a typical application -- an OC48 packet-over-Sonet line card, for example -- would require more than 60 chips using silicon from Agere, while a similar implementation with his company's silicon requires only four chips: one SpeedRouter, one SpeedAnalyzer, and two SDRAMs (an inexpensive type of memory chip). Agere disputes these numbers, saying there is no such thing as a "typical" application.

Chip numbers aside, IP Semiconductors may have gained an edge over other vendors in this space by virtue of the architecture it's adopted. Most network processors today are based around one or two "processor cores" (CPUs, essentially), with a set of program instructions to tell them what to do.

In contrast, IP Semiconductor has designed its chips around an FPGA (field-programmable gate array) from Xilinx Inc. (Nasdaq: XLNX). FPGAs deliver better performance than processor-based products because, once programmed, the chip instructions are effectively hard-wired. The downside is that FPGAs are not as easy to upgrade or modify as processor-based solutions.

— Pauline Rigby, Senior Editor, Light Reading
skeptic 12/4/2012 | 7:58:25 PM
re: Startup Claims Processor Breakthrough
So if the answer to high-speed packet processing
is just to go buy FPGAs from Xilinx?!?, then
the reasonable conclusion is that there is
no longer a market for high-speed packet
processing chips at all. And that this
company (among other things) is annoucing
that they have no real market for what they
have developed.

I tend not to believe that.

The price paid for using FPGAs is usually that
the processing done has to be very simple.
I guess you could string a couple CAMs and
an FPGA together and do a reduced set of
processing functionality, but is that going
to be good enough for anyone to actually make
a product out of?

And if its that simple, the router companies
will build the packet processor themselves.
xinant 12/4/2012 | 7:58:16 PM
re: Startup Claims Processor Breakthrough Hi

Actually it is Ok to try this approach.

Basically there are three general ways to attack
the NPU:

1) ASIC ;
2) Configurated architectures (maybe based on FPGA);
3) Massivelly parallel machines (maybe based RISCs)

However, none of them is perfect. As you pointed
out, approaches (1) and (2) can only do simple
things but (3) cannot match the performance of

The real question to (2) is how can they compete
with (3) in terms of application domains and easy
of programming? It is already hard to programe an
application in the assembly language not alone
Verilog/VHDL which is required in (2).


gewing 12/4/2012 | 7:53:32 PM
re: Startup Claims Processor Breakthrough In production now -


Entridia is the only company to demonstrate back-to-back 40 byte packets at wire-speed. They demoed this at Supercomm, June 2001.

Yes, it's an ASIC.
nanette 12/4/2012 | 7:53:03 PM
re: Startup Claims Processor Breakthrough The SPEEDRouter FPGA Network Processor is a full-duplex 2.5 Gbit/s FPGA based packet processing
engine targeted for Xilinx Vertex series of FPGAs.
Programming of the SPEEDRouter is done using templates in Verilog, which is a programming language that most design teams of high end routers are familiar with (as opposed to developing microcode software for multiprocessor architectures).

The SPEEDAnalyzer is a fully programmable lookup and classification ASSP. The VLIW microprocessor engine of the SPEEDAnalyzer uses patent pending execution units to perform lookup / classification / policing tasks for the SPEEDRouter and employs SDRAM for table storage. A lookup algorithm in the SPEEDAnalyzer is done in a few instructions and does not require
hundreds of instructions (and development time).

After having considered all the options for designing high-speed Network Processor solutions we developed the SPEEDRouter FPGA based Network Processor with the SPEEDAnalyzer SDRAM based VLIW
microprocessor lookup engine in light of:

1) Flexibility

The solution offers a level of flexibility that no
FSM or CAM can match. Router vendors are free to
implement any search algorithm, with any number of
fields, on packets of any size, and in networks of any Layer 3-7 protocols. The FPGA Network Processor supports the largest base of industry standard interfaces as well as any custom interfaces needed.

2) Performance

Our lookup speed and packet throughput are superior to RISC microprocessor and standard NPUs.
Thanks to the patent pending VLIW microprocessor, our users will experience lookup and classification completed in only a few instructions, as opposed to tens or hundreds.
Our cut-though datapath of the SPEEDRouter minimizes latency and jitter.

3) Power and Device Cost

Our solution provides considerable cost savings for equipment makers when eliminating store-and-forward and the use of SRAM/CAMs. Our device count and power consumption are 5 times lower than any other similar solution.

Please visit our web site www.ipsemiconductors.com for more info on our products.
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