SLE announced the development of a licensable Interlaken protocol IP core for use in ASIC or FPGA designs
January 23, 2007
EAU CLAIRE, Wis. -- Silicon Logic Engineering Inc. (SLE), a high-end semiconductor design services division of Tundra Semiconductor Corporation today announced the development of a licensable Interlaken protocol IP core for use in ASIC or FPGA designs.
SLE’s Interlaken IP Core is scalable, with early versions providing from 10Gbps to 60+Gbps bandwidth across the interface. Future versions will provide over 120Gbps of bandwidth. This scalability ideally suits Interlaken for multiple generations of future network switches, routers and storage equipment. The scalability is achieved through the combination of the SERDES speed (3.125Gbps to 6.375Gbps) and a variable number of SERDES lanes (1 to 24).
Tundra Semiconductor Corp. (Toronto: TUN)
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