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Trio Builds Interface Chip

Altera, Sarance, and Cortina announced the availability of the industry’s first FPGA-based Interlaken intellectual property core

August 14, 2006

2 Min Read

SAN JOSE, Calif., SUNNYVALE, Calif., and OTTAWA -- Altera Corporation (NASDAQ: ALTR), design services provider Sarance Technologies and communications semiconductor specialist Cortina Systems today announced the availability of the industry’s first FPGA-based Interlaken intellectual property core to speed design of network systems applying the Interlaken protocol.

The Interlaken protocol IP core, created by Sarance Technologies, lets communication and storage network equipment developers apply the new interconnect specification using Altera® Stratix® II GX FPGAs. Together, the IP and FPGAs enable more cost-effective solutions for 10-, 20-, and 40-Gbps interconnect designs in next-generation network switches, routers and storage equipment.

“Our IP is a complete solution that enables customers to rapidly deploy Interlaken-compliant technology in high-performance applications using Altera’s Stratix II GX FPGAs,” said Farhad Shafai, vice president, R&D at Sarance Technologies. “The IP provides all of the robustness and scalability of Interlaken using a minimum amount of FPGA resources. The core is comparable in size to existing Service Packet Interface Level 4 (SPI-4.2) solutions for 10 Gbps applications. By applying this Interlaken-compliant core on programmable logic devices, developers can immediately begin new designs incorporating this protocol specification.”

The Interlaken protocol is a royalty-free specification jointly developed by Cortina Systems and Cisco Systems for makers of high-performance network components and equipment. The specification builds upon the logical structure of SPI-4.2 interface technology, now widely used in networking equipment. It preserves the capabilities of SPI-4.2 with multiple logical channels and back-pressure information, while eliminating its bandwidth ceiling and curtailing associated pin-count cost. Interlaken’s 90 percent chip-to-chip signal trace improvement increases performance and reduces both board and chip design costs.

“The Interlaken protocol eliminates the cost and performance barriers of existing interconnect standards by taking advantage of high-speed, multi-channel serial interconnect technology to enable the highest density networking equipment,” said Zino Chair, vice president of marketing at Cortina Systems. “Altera FPGAs, with their outstanding multi-gigabit transceiver technology, provide an exceptional platform for realizing the potential of the protocol.”

Interlaken allows greater integration in network system designs by providing a framework for channelized packet interfaces built upon a flexible and highly efficient serialization/de-serialization (SERDES) physical layer. Using the latest 6.375-Gbps SERDES technology enables interface designs that scale from 10 to 100 Gbps and beyond.

“This partnership results in IP enabling communications systems designers to cost-effectively support chip-to-chip communication above 10 Gbps,” said John Sakamoto, senior business unit director at Altera. “Our Stratix II GX SERDES supports speeds from 622 Mbps to 6.375 Gbps and provides flexible bonding options that maximize the advantages of the Interlaken protocol.”

Altera Corp. (Nasdaq: ALTR)

Sarance Technologies Inc.

Cortina Systems Inc.

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