Project Challenges Network Processors
The project, called PIPPIN for Programmable IC Platforms for Programmable IP Networks, has just gotten underway at Queen's University of Belfast in Northern Ireland.
The problem with microprocessors in general is that at any one time only 5 percent of the transistors are doing anything useful, explains project leader Professor Alan Woods. Using FPGA technology, he reckons it will be possible to increase that utilization to a more respectable 60 to 80 percent.
That extra computing muscle could be used in a couple ways: simply to pack more performance into less space or, more creatively, to allow optical networks to be reconfigured according to the demand on the network at the time. Professor Alan Marshall, also from Queen's University, is collaborating on the networking aspect of the project.
As the first stage, Woods and his students have been looking at ways of reducing the time it takes to reconfigure FPGAs. "We have been doing reconfiguration where the amount of time it takes to reconfigure is zero," he says. (As a scientist, he really means zero, not just an infinitesimally small amount of time, by the way.)
But how? Before delving into the details, here's a bit of background.
FPGAs, which are Xilinx's bread and butter, are integrated circuits containing thousands of identical logic cells interconnected by a matrix of wires and programmable switches. Complex circuit designs can be implemented simply by specifying the simple logic function for each cell and selectively closing the switches in the interconnect matrix.
Getting the configuration information onto the chip takes time, of course, even if it's only a few milliseconds. But there is another way.
Configurable chips perform different functions in different areas of the chip, using a multiplexer to select between them. Both functions are already present, so it takes no time to make the switch.
FPGAs contain multiplexers, loads of them in fact, because they are used to load the configuration information onto the chip. "We asked ourselves: Can we be clever, and take the circuitry that was put in there for programming, and use it in a completely different way?" says Wood.
Multiplexers could be used to switch between different functions on the FPGA instantly, while the parts of the chip that would otherwise lie inactive can be reconfigured and ready for the next set of computations.
Are network processor vendors concerned? Well no, says Robin Melnick, director of marketing with chip maker Applied Micro Circuits Corp. (AMCC). "While interesting, this new potential development would do little to make FPGAs a more attractive alternative to NPUs," he contends.
"Yes, FPGAs can be reprogrammed, but that's low-level logic design, not high-level application software. And, as with ASICs, the FPGA customer would still have to do a new hardware design for each new application as well as redesign the drivers.
"With NPUs, on the other hand, application programming can be done in high-level languages making use of built-in network packet/cell processing and traffic management facilities. Vendors such as AMCC also provide off-the-shelf application software for ATM, IPv4/v6, MPLS, and so on, so customers often create very little new code, allowing them to focus more closely on their own differentiating features."
It's also worth pointing out that the FPGA project has only just gotten underway and is expected to take three years to reach the demonstration phase. The funding for the project was not specified.
— Pauline Rigby, Senior Editor, Light Reading