SAN JOSE, Calif. -- Paion, a privately held company specializing in design and development of high-performance networking chipsets, today announced two new products in its gigabitPLUS series of gigabit Ethernet switching products. The announcement includes a powerful and fully programmable Network Processor with multiple on-chip processors and a companion switch fabric. Paion’s innovative architecture allows OEMs to design systems that scale to well over two hundred Gigabit Ethernet ports, all offering wirespeed communications capabilities and minimum latency in Layer 2/3 (and higher) switches. The products are supported with a complete set of software development tools including a C-compiler, debugger, profiler, and application rule compilers. Paion also provides numerous firmware library routines, reference code, and a sample routing engine for the host processor. "Paion's focus [with this NPU/fabric solution] on Ethernet and its complete PHY-to-PHY solution addresses the needs of many vendors around the world. It is especially attractive to OEMs in Asia where Paion is the only announced NPU vendor" said Linley Gwennap, President and Principal Analyst of industry-watchers - 'The Linley Group.' Gapseong Noh, Paion’s CEO, added “The capabilities of this chipset will allow our customers to build systems with the latest advanced features in Ethernet switching - like security screening, QoS, and MPLS - while still offering the high performance demanded by their users." Paion has developed these chips for use by OEMs in building state-of-the-art Ethernet switches. They work together in a variety of configurations ranging from simple Fast-Ethernet-to-Gigabit-Ethernet uplinking all the way to complex multi-stage non-blocking 256-port switches with 512 Gbps throughput. All configurations give wirespeed performance with dramatically minimized latency while avoiding Head Of Line (HOL) blocking. Paion