HyPHY puts multiple protocols onto OTN and is intended for P-OTS boxes. META is meant for Carrier Ethernet switch/routers and handles only Ethernet traffic, but its job is similar: to groom that traffic for transport over the OTN network. In other words, the Ethernet box becomes capable of handing off an OTN stream.
Why the obsession with OTN, rather than running Ethernet throughout the network? It has to do with the whole packet/optical convergence thing. Carriers that already want OTN in the middle of the network like the idea of spreading OTN's reach further. "The pull for having OTN capability even on the packet boxes is so you can have a unified management layer," says Babak Samimi, a PMC director of marketing.
Cores are fragments of chip designs that are meant to go into other chips. Avalon doesn't sell any chips itself, but sells cores for use inside an Field Programmable Gate Array (FPGA) or Application-Specific Integrated Circuit (ASIC).
Avalon's star exhibit was a complete virtual Application-Specific Standard Product (ASSP) that can be a transponder, a muxponder, a regenerator, or an add-drop multiplexer. As a product, the chip isn't meant to do all those things all the time; Avalon customizes it by subtracting whatever functions aren't needed.
One advantage to that method is that by completing chip validation on the entire ASSP, customized versions will come pre-validated, in a sense, saving time in the design process. That validation step has been a stumbling block for core vendors, says Niki Pryor, Avalon's product manager.
Avalon is an interesting company, if only for being based in Newfoundland. ("The Hawaii of the north Atlantic," says Alfred Whiffen, vice president of sales and marketing.) The company faces competition from the likes of Tpack A/S and Xelic Inc. .
At Supercomm, the company showed FPGAs acting as 100-Gbit/s framers for Optical Transport Network (OTN) or as 40-Gbit/s packet processors, essentially taking the job of a network processor.
The latter case is particularly interesting. "We're starting to see the chinks in the armor of the ASSP for packet-processing functions," says Arun Iyengar, director of Altera's communications group.
Mostly it has to do with power consumption. First, in order to please multiple markets, chipmakers are stuffing more functions into the chips, making them eat more power. Second, FPGAs have been pushing the limits of chip-manufacturing processes, so that their chip elements are smaller and less power-hungry. (Altera and Xilinx Inc. (Nasdaq: XLNX) are working at the 40nm node, if you want to get all chip-geeky about it.)
The result is that FPGAs can sometimes do the work of a network processor without using as much power, Altera claims. "If you'd followed the FPGA industry for a long time, you'd say that's unheard of," Iyengar says.
Light Reading happened to find one taker for the FPGA-as-network-processor idea: the rejuvinated Hyperchip Inc. (See Supercomm: Hyperchip Returns, Gets Small.)
— Craig Matsumoto, West Coast Editor, Light Reading