Ciena Pushes Ahead to 400G
The WaveLogic 3 chip promises to extend 100Gbit/s reach to 2,500 km without regeneration, through technologies including soft forward error correction (FEC).
The chip also uses a digital signal processor (DSP) on the transmit side. This opens the possibility to mess with 100Gbit/s wavelengths, squashing them into a space smaller than the usual 50GHz spacing, so that more wavelengths can fit on a fiber.
WaveLogic 3 also takes advantage of increased processing smarts. For example, it can be programmed to make tradeoffs -- improving latency by lightening up on FEC, and therefore giving up some reach.
Ciena expects to have customers running live traffic on WaveLogic 3 this year.
Why this matters
This means the 400Gbit/s generation is almost underway, although Ciena expects it to happen in a limited fashion and doesn't expect customer deployments until 2013.
The real importance is on the 100Gbit/s side, where longer reach and lower power are going to be key topics this year. Cisco already declared the ability to run 100Gbit/s wavelengths for 3,000 km without regeneration, as EANTC verified in its recent test of Cisco CloudVerse, and we'll probably hear plenty more about 100Gbit/s improvements during OFC/NFOEC next week.
A couple of other things to note: Ciena will continue using an in-house chip for its next 100Gbit/s generation, showing the power of vertical integration.
And with the transmit DSP, and the ability to squeeze more wavelengths together, it's setting up applications for flexible-grid reconfigurable optical add/drop multiplexers (ROADM)s in the 100Gbit/s generation. It's suspected that a flexible grid will be useful as the industry approaches 1Tbit/s.
Ciena put together this video to show the thing in action:
Keep up with our coverage on the Light Reading OFC/NFOEC site.
— Craig Matsumoto, Managing Editor, Light Reading