BertScope Adds SSC
SyntheSys introduces Spread Spectrum Clock and data generation for the BertScope S Signal Integrity Instrument Family
January 30, 2007
MENLO PARK, Calif. -- SyntheSys Research, Inc. a developer and manufacturer of high-speed signal integrity test and measurement solutions for the computer, storage, and communications industries, introduces Spread Spectrum Clock and data generation for the BERTScope S Signal Integrity Instrument Family.
Spread Spectrum Clocking (SSC) is being used by many of the latest high-speed serial buses in order to reduce EMI issues in new board and system designs. Data patterns with embedded SSC and SSC full and sub-rate clocks are needed in order to fully test and characterize ICs and boards in systems using SSC. Customers need compliant SSC data streams for qualifying their devices and to determine performance margins by being able to generate SSC data in excess of specification limits.
BERTScope S with Option SSC accelerates time-to-market for developers and manufacturers of integrated circuits and boards for SATA, PCI-Express, FB-DIMM and next generation SAS by providing easy-to-use programmable SSC clocks and data together with uncompromised integrated stress generation for fast device compliance and margin testing.
SSC is available up to 8 Gb/s – well beyond the maximum data rate of 6 Gb/s of many standards planning to use SSC.
SSC levels can be easily adjusted from zero to required compliance levels, and up to levels more than double the levels that current standards require.
SSC frequency can be easily adjusted well beyond the required 30-33 kHz range. SSC modulation may be applied in three different ways, down-spread (for example -5000 ppm for SATA and PCI-express), center-spread (+ or
5000 ppm required by future SAS standard), or up-spread. BERTScope S’s full range of jitter (SJ, RJ, and BUJ) may be added to SSC data without limitations for complete device stress testing. Included are BERTScope S’s outstanding signal integrity analysis tools
BER-correlated eye diagram, jitter peak, BER contour, Q-Factor, jitter tolerance, mask testing and patented error location analysis.
BERTScope S with Option SSC may be paired with a BERTScope CRJ or CR for compliant clock recovery and to calibrate test signals at the point of test. In addition, the SSC modulation on the data from either the BERTScope S generator or from a device under test may be displayed and analyzed. When paired with the new BERTScope CRJ the BERTScope S also provides jitter spectrum analysis and duty cycle distortion measurement.
Price and Availability
The BERTScope S Option SSC is $9,000.00 and is available on BERTScope S 12500B and 7500B. Delivery time is 8 weeks ARO.
SyntheSys Research Inc.
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