Inphi Tests BER

Introduces a 28G Bit Error Ratio (BER) receiver reference design

January 20, 2009

2 Min Read

WESTLAKE VILLAGE, Calif. -- Inphi® Corporation (, the world leader in analog performance and signal integrity, today introduced a 28G Bit Error Ratio (BER) Receiver reference design. This reference design will be highlighted this week in Inphi’s booth # 2-57 at the Fiber Optics Expo in Tokyo, Japan, January 21 – 23, 2009. The 28G BER Receiver is for R&D or production testing of emerging high speed protocols from 13 to 28 Gbps, including 100 Gigabit Ethernet, 40G Differential Quadrature Phase Shift Keying (DQPSK), 14G Fibre Channel, and 100G Dual-Polarization Quadrature Phase Shift Keying (DP-QPSK). The reference design helps to accelerate time-to-market for Test & Measurement vendors designing next generation 28G test platforms.

For high speed data links, BER testing is the most fundamental test at the physical layer, as it measures whether the data bits are correctly transmitted across the link. BERT systems for speeds up to 12.5 Gbps are well established. However, with the emergence of networking standards such as 40G SONET, 100G Ethernet, and 14G Fibre Channel, design and test engineers require BERTs with high speed front-ends above 12.5 Gbps, up to 28 Gbps. The Inphi 28G BER Receiver reference design addresses the challenge of designing a high speed front-end at 28 Gbps, and integrates an Inphi chipset in a proven, high performance, and reliable design. The reference design, together with a 12.5G BERT and a 28G high speed test pattern generator, comprise a complete 28 Gbps test solution. For test applications requiring clock recovery, the 28G BER Receiver reference design provides a buffered copy of the high speed input data stream, which can be supplied to an optional Clock Recovery Unit to generate a recovered clock. The 28G BER Receiver reference design is based on an Inphi chipset of a 5081DX 50 Gbps 1:4 Demultiplexer, 25717CF 25 Gbps 1:2 Fanout, and 20709SE 20 Gbps 2:1 Selector.

“Inphi’s 28G BER Receiver reference design is a simple and cost-effective tool for the development and testing of emerging higher speed interfaces,” said Mark Donovan, Vice President of Optical Assemblies for Finisar Corporation. “This reference design enables us to improve our test capabilities while leveraging existing investments in 12.5G BERT systems and software.”

Inphi Corp.

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