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Comms chips

Next Gen Sonet: What About SDH?

Plenty of vendors have brought out next-generation Sonet chips in the past few months, paving the way for data traffic to be carried more efficiently over existing carrier infrastructure.

Some of these chips also claim to support SDH, the transport protocol used in telecom networks everywhere outside North America. But everyone's dirty little secret is that, in fact, they can't support next-generation SDH as effectively as they can support next-generation Sonet.

That is, until yesterday, when startup West Bay Semiconductor Inc. announced its WB4500 virtual concatenation framer (see West Bay Ships Sonet Chip). The startup claims it has the only chip that brings the full benefit of the virtual concatenation technique -- a key element of next-gen Sonet -- to SDH.

Why? There are two issues: encapsulation protocols and granularity. Time to dig into the details.

Encapsulation

For starters, there's the issue of the best way to encapsulate packets for transportation over an SDH network. The Yanks have pretty much decided to do this using a protocol called generic framing protocol or GFP. GFP supports both Sonet (Synchronous Optical NETwork) and SDH (Synchronous Digital Hierarchy), in theory.

Unfortunately, life isn't so simple outside America. Other countries are insisting on support of an alternative called link access protocol–SDH or LAPS (see Next-Gen Sonet ).

LAPS is a required standard in China -- a huge potential market for SDH equipment -- so vendors that don't support it won't get very far selling out there, says West Bay's president and CEO Tino Varelas. LAPS is also on the rise in Europe. Even if it's not a requirement, supporting the "local" standard helps network equipment manufacturers feel more at ease, he adds.

West Bay's WB4500 supports LAPS, as do the HDMP3002 from Agilent Technologies Inc. (NYSE: A) and the EtherMap48 from TranSwitch Corp. (Nasdaq: TXCC). Both the Agilent and TranSwitch chips were also announced yesterday (see Agilent Intros Sonet Chip and TranSwitch Expands EOS Line).

However, support of LAPS is not enough, says Varelas. The other issue is:

Granularity

In the Sonet world, virtual concatenation involves glomming together the smallest channels -- STS1s (51.8 Mbit/s) -- to make suitably sized pipes for the particular service to be carried. There's no direct equivalent in the SDH world, where the smallest channels, called AU4s, are three times the size –- 155 Mbit/s. (For more on this issue, see: Tutorial on Grooming Switches.)

As a result, vitual concatenation provides a less efficient solution for SDH than it does for Sonet. For example, a Fast Ethernet (100 Mbit/s) channel can be carried by two Sonet STS1s, thus occupying nearly 100 percent of the bandwidth. In SDH, however, putting a Fast Ethernet channel into 155 Mbit/s results in only 67 percent bandwidth utilization.

West Bay says it overcomes this problem by building a chip that can see down to the VC3 level. The VC3 is the same size as an STS1 but is hidden by several layers of protocol origami. Each VC3 must be mapped into what's called a TUG3, and then three of them are combined to form a unit called AU4. West Bay's chip can deal with these complexities without worrying about the bizarre math that adds up three and gets four.

The upshot is that West Bay claims to offer the only sensible solution for virtual concatenation outside America -- although Transwitch is also claiming virtual concatenation at the VC3 level in its product announcement today.

Competitors

Inside America, West Bay's closest and most serious competitor is probably Agere Systems (NYSE: AGR). Agere is the incumbent in virtual concatenation chips and is the only company shipping product right now (see Agere Produces Sonet Framer Chip).

Many of the other wannabe vendors in the virtual concatenation space -- namely Agilent, Cypress Semiconductor Corp. (NYSE: CY), and PMC-Sierra Inc. (Nasdaq: PMCS) -- have chosen to optimize their chips around the specific application of sending Gigabit Ethernet over Sonet. PMC-Sierra and Agilent, for example, have integrated the Ethernet MAC (media access controller) with their framers, which has the advantage of allowing them to interface directly with optics.

West Bay and Agere, on the other hand, have opted for something more flexible. They are targeting a wider range of applications such as aggregation and multiservice provision platforms. Both include an STS1-level crossconnect that can groom TDM (time-division multiplexed) traffic before sending it off across the network.

A distinguishing factor from the competition, says West Bay, is that its chip supports up to 48 independent logical channels, which can each carry different protocols -- including Asynchronous Transfer Mode (ATM), packet over Sonet, GFP, or LAPs -- simultaneously.

"For many applications, the only chip that will work is the West Bay chip," boasts Varelas. If a customer wants to aggregate Fast Ethernet channels, for example, then he or she will need the West Bay chip because it is the only one that supports enough logical channels, he says.

For comparison, Agilent and TranSwitch say their chips support four channels. Agere did not respond to calls.

West Bay expects samples of its chip to be ready in the third quarter. The WB4500 is priced at $475 in quantities of 1,000.

— Pauline Rigby, Senior Editor, Light Reading
http://www.lightreading.com

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