Xilinx announces interoperability of its Virtex-II Pro 3.125 serial transceivers with IBM's High Speed Serdes (HSS) core

December 23, 2003

1 Min Read

SAN JOSE, Calif. -- Xilinx, Inc. (NASDAQ:XLNX) today announced successful interoperability testing of the IBM High Speed SERDES (HSS) core with Xilinx's Virtex-II Pro 3.125 serial transceivers. With Xilinx FPGAs and IBM ASICs often on the same boards, the interoperability testing significantly reduces overall product time-to-market by allowing customers to focus on design issues rather than verifying electrical compliance. Applications now enabled include high-speed interface requirements for Fibre Channel, PCI Express, Serial Rapid I/O, Serial ATA, Serial Attached SCSI, 10Gb Ethernet, and OIF interfaces.

"The interoperability of the IBM and Xilinx SERDES cores, coupled with Xilinx's industry standard interface compliance is a testament to the robustness of the two company's SERDES designs," said Bill Van Duyne, director of Field Applications for IBM Microelectronics. "IBM ASIC customers will find that not only do Xilinx FPGAs lend themselves to needed board logic, they can also extend ASIC product life-cycles given their flexibility which allows additional functionality to be added later."

"IBM SERDES interoperability with Xilinx high-speed serial transceivers is key to ensuring the confidence of designers who need to add the flexibility of a Xilinx FPGA to complement their ASIC design," said Jerry Banks, director of Global Alliances at Xilinx. "Interoperability testing now reduces the need for interoperability testing later in the design cycle."

Xilinx Inc.

IBM Corp.

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