NurLogic Launches PLLs

Delivers family of phase locked loop -- PLL -- high-speed analog intellectual property ranging from 266 MHz to 4.8 GHz

July 30, 2001

1 Min Read

SAN DIEGO -- NurLogic Design, Inc., a developer of high-bandwidth connectivity solutions, today announced its family of high-performance Phase Locked Loop (PLL) analog intellectual property (IP) for implementation into complex high-end communications, graphics and microprocessor designs. NurLogic's extensive set of pre-developed, high-performance PLLs are generated for leading TSMC, IBM, and UMC standard CMOS process technologies from 0.25-micron to 0.13-micron, and range from 266 MHz to 4.8 GHz. NurLogic offers the most extensive group of PLLs available in the industry. Analog timing functions such as advanced PLL technology are becoming a key design element to manage system clocking and achieve the highest system performance. NurLogic's analog PLL IP is based on the company's advanced patent-pending architecture that enables very high speed with minimal jitter. Very low jitter helps to maximize clock frequency and operating speed. According to Michael Brunolli, chief technical officer for NurLogic Design, Inc., "NurLogic's significant analog design expertise and tremendous first pass design success with our analog timing IP cores make us uniquely positioned to address this segment of the market. Our customers in the high-performance communications and high-end computing markets depend upon NurLogic to deliver key analog IP for their next-generation products. Our breadth and quality of analog IP is unparalleled in the industry." NurLogic Design Inc.

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