IBM Chips Go 3D

IBM creates new dimension for high-performance chips with a new technique for building three-dimensional integrated circuits

November 11, 2002

1 Min Read

YORKTOWN HEIGHTS, N.Y. -- IBM today announced that it has developed a new technique for building three-dimensional (3D) integrated circuits (ICs) that will help increase chip performance, functionality and density. This technique is an essential step toward successful realization of high performance 3D ICs.Today's microchips are two-dimensional: the transistors are in one plane and a multi-layer system of wires is used to connect different parts of the chip. Opening up a third dimension for integrated circuits creates new opportunities to increase chip performance, functionality and device packing density by

  • reducing the length of the wires that connect transistors and increase bandwidth between logic and memory,

  • facilitating the integration of heterogeneous materials, devices, and signals, such as placing electrical and optical devices on different levels of the same chip,

  • and putting more transistors on a given chip.

"Traditionally, decreasing transistor size and wire lengths produces faster, more powerful chips," said Dr. John Warlaumont, Director of Silicon Technology at IBM Research. "However, it is becoming more difficult to reap performance gains from these traditional 'scaling' techniques because the transistor dimensions are reaching fundamental physical limitations. IBM's development of this new technique for building 3D integrated circuits opens new avenues for chip performance improvements."IBM's new technique for building 3D ICs based on the layer transfer of completed circuits involves transferring functional circuits (many transistors and several wiring levels) from one wafer to another and connecting the multiple layers electrically to form the 3D chip. The key to this transfer is a wafer-level bonding approach that joins high performance device layers fabricated by conventional means. IBM Corp.

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