SOMERSET, N.J. -- Multilink Technology Corporation (Nasdaq: MLTC), a leading provider of advanced semiconductor-based solutions that accelerate the deployment of high-speed optical networks, today introduced their next generation, 10 Gb/s, Enhanced Forward Error Correction (EFEC), digital wrapper processor device; the MTC6134. This single chip, bi-directional transport device features full SONET/SDH section and line overhead processing, 10 Gb/s Ethernet performance monitoring and G.709 Digital Wrapper termination and generation for 10 Gb/s systems. The EFEC advantage provides Metro applications with over 8.5dB of net coding gain at 1x10-15 corrected BER, based on a successful approach used by the MTC6131 SuperFEC, and only 3.5 watts of power dissipation. The MTC6134 FEC device provides superior error correction of arbitrary data streams of 10 Gb/s in data and telecom networks and can significantly extend the reach of metro optical systems. Error correction is provided based on a block oriented Reed-Solomon code RS(255,239) in addition to an optional proprietary FEC code that provides increased net coding gain with the same 7% overhead. Integrated overhead processing makes it especially suitable for OC-192/STM-64 SONET/SDH and 10 Gb/s Ethernet transport applications. The device also supports single chip RS FEC to EFEC bridging and RS FEC to RS FEC regeneration. "We are excited to introduce our third generation of advanced forward error correction devices. The net coding gain and robust feature set coupled with extremely low power dissipation presents an integrated chip that outperforms other Metro offerings," said Dr. Richard N. Nottenburg, President, Chief Executive Officer and Chairman. Multilink Technology Corp.