Motorola Spruces Up C-Port Chip
In an announcement timed to coincide with the Network Processors Conference in San Jose, Calif., today, Motorola launched an upgraded version of the C5, called the C5e, and an accompanying traffic manager chip. It also drew back the veil on its OC192 (10 Gbit/s) product roadmap (see Motorola Has a Roadmap).
But first a little history. When Motorola bought C-Port it acquired one of the first OC48 (2.5 Gbit/s) network processors on the market. That chip has notched upwards of 60 design wins at companies including Atoga Systems and Extreme Networks Inc. (Nasdaq: EXTR).
The chip came under fire, however, because reportedly it could only process multiple OC12s, rather than a true OC48 channel.
Hidden in today's announcement is an innocuous little chip called an M5 channel adapter that purports to fix this oversight. This is a piece of logic that adds wire-speed OC48 and OC48c interfaces to the C5 and C5e.
"We've always been able to offer [OC48], it's just that it required a little more work on the part of our customers," says Bob Gohn, VP of Marketing for Motorola's C-Port product line. In the past, customers had to develop the glue logic themselves.
Competitors are still skeptical, however. Whether the C5 can really handle OC48 depends on how well the microprocessor cores share information, says Robert Munoz, product line manager for network processors at Agere Systems (NYSE: AGR).
The reason that the C5, on its own, can only handle multiple OC12s stems from its architecture. The C5 contains 16 processing units (C-Port calls them "channel processors"). Each port links to exactly one processing unit, and the units aggregate in groups of four. The architecture remains fundamentally the same in the upgraded version of the C5, the C5e.
Detailing the specific improvements in the C5e, Gohn said, "We've got additional headroom for more performance, even at the same clock speed."
Motorola claims to have boosted table lookups from 13 million to 46 million per second. "That's five times what you need for OC48," he says. The extra overhead this provides can be used for higher-level functions. Further gains are made by increasing the clock speed from 200 to 266 MHz. Finally, the chip is fabricated in 0.15 micron CMOS technology, rather than 0.18 micron, resulting in a drop in power consumption from 17W to just 9W.
Motorola will be making architectural changes in its OC192 chip, however. The C10, details of which were discussed for the first time at the conference, will be available in Q2 2003, with the software development kit on offer about a year earlier. As its name suggests, the C10 will have twice the throughput of the C5; in other words, it will be a half-duplex OC192 solution.
Gohn says that Motorola opted to upgrade its OC48 chip in preference to making a big push to get an OC192 chip out there. "For us, the money is on attacking problems in the edge and access network," he says. "There are not a whole lot of OC192 ports out there. We see the volume in OC48 for some time to come."
The big change for the C10 will be the addition of a small switching fabric at the front of the chip that will allow any port to connect to any channel processor. In other words, the change is targeted right at the problem of helping microprocessor cores communicate with each other.
— Pauline Rigby, Senior Editor, Light Reading