Motorola Breakthrough Makes Waves
The multinational firm announced this week that its scientists have come up with a way -- albeit by accident -- that makes it possible to "grow" gallium arsenide (GaAs) on top of a silicon wafer (see Motorola Makes Materials Breakthrough ). Working together with epitaxial wafer vendor IQE PLC, Motorola created a 12-inch (300mm) GaAs-on-silicon wafer, which is twice the diameter of the largest GaAs wafers available today. The breakthrough could significantly reduce the costs of substrates and processing for gallium arsenide, the company claims.
Simply put, Motorola has found a way to combine the robustness and low cost of silicon processing with the superior optical and electronic properties of so-called "compound semiconductors" such as gallium arsenide and indium phosphide.
The details of how this was achieved are complicated. To give an idea of how complicated, try this: Motorola says it has filed no fewer than 270 patents on the new technology!
However, the basic principle is easier to understand. It boils down to the fact that semiconductors are essentially single crystals. When depositing a thin layer of one material on top of another, the integrity of the crystal is maintained at the boundary, even though the lattice constant (the distance between atoms in the crystal) may be different. This creates stress.
As the thickness of the layer grows, at some point the stress in the crystal is relieved by generating atomic-level cracks. These are bad news because they degrade the electrical and optical properties of the material. This is what normally happens when people try to grow gallium arsenide on silicon.
The key to this problem cropped up unexpectedly. Motorola scientists were using an oxide, strontium titanate (STO), to develop ultra-thin transistors. They found that oxygen diffused through the STO layer, forming an "amorphous," or random, interface between the STO and silicon.
At first, the scientists thought this was a nuisance. Then one of them, Dr. Jamal Ramdani, realized that the amorphous layer removed the strain from the STO, allowing it to relax back to its natural crystal lattice constant. What's more, the lattice constant of the STO was close to that of GaAs, allowing the two materials to bond without cracks.
It's worth pointing out that other companies have tried to solve the same problem in different ways. Nova Crystals Inc. has developed a low-temperature bonding process. And AmberWave Systems Inc. is reported to be working on an interface layer of graded silicon germanium. But these approaches appear to have significant disadvantages compared to the technique Motorola has pioneered, says Jim Prendergast, director of Motorola's physical sciences laboratory.
The most immediate impact of this development will be on high-speed electronic chips, says Asif Anwar, an analyst with Strategy Analytics in the U.K. Gallium arsenide is used in the communications industry to make laser driver and modulator driver chips, for example, that work at OC192 (10 Gbit/s) serial data rates. It's not possible to use silicon in this application because the electrons in silicon are too sluggish.
Several things could happen, says Anwar. For starters, "middle-ground" technologies such as silicon germanium (SiGe), which is also used to make OC192 chips, could be squeezed out. SiGe is cheaper than gallium arsenide but its performance isn't as good. "If people can get GaAs performance at the same or lower cost than SiGe, then SiGe will go to the wall," he says.
Another possibility is that chip makers with experience in analog circuits, such as National Semiconductor Corp. (NYSE: NSM) and Texas Instruments Inc. (NYSE: TXN), could use this as an opportunity to break into the high-speed chip market. They could license the wafer technology from Motorola and turn over one of their existing 12-inch silicon wafer plants to the production of GaAs-on-silicon chips.
Motorola says it's trying to repeat the feat by producing indium phosphide (InP) on silicon. "If you could grow InP on 12-inch wafers, that would really shake things up," says Anwar. "InP is the main driver for OC768 [40 Gbit/s] transmission."
Another vision that's firmly in the sights of the Motorola researchers is the possibility of integrating both optical and electrical functions on the same chip, using the silicon side of the wafer for standard electronics and the InP side for fast electronic and optical devices.
Questions still remain, however. The biggest one is about manufacturing yields. Process yields in compound semiconductor manufacturing are notoriously low.
— Pauline Rigby, Senior Editor, Light Reading