Fujitsu Offers ASIC Widget

2.5-Gbit/s transceiver macro designed for high-bandwidth data-communications ASICs

May 23, 2001

1 Min Read

SAN JOSE, Calif. -- Fujitsu Microelectronics, Inc. (FMI)today announced a new triple-mode physical I/O transceiver interface macrofor use in complex system-on-chip (SOC) ASIC designs for high-end networkingapplications. The new macro provides data transfer rates of 2.5 Gbps, 1.25Gbps and 622 Mbps, which can be selected based on system requirements. Ithas been developed specifically for products like add-drop multiplexers,broadband cross-connects, fiber optic terminators and test equipment, andsystems equipment built using Wavelength Division Multiplexing (WDM).The new parallel transceiver macro, which is available as a core librarycell for ASIC design, provides a 16-bit transmitter and 16-bit receiverarray. Each receiver bit includes a Clock Data Recovery (CDR) with analogand digital phase locked loop. The receiver also includes an integrated lineequalization capability, which compensates for inter-symbol interferences,and equalizes losses up to 12 dB. The macro incorporates an on-chip 50 ohmtermination resistor for receiver and transmitter, along with PRBSgenerators and a comparator, for easy testing. Power dissipation atoperating speeds of 2.5 Gbps is less than 2.5W for the 16-bit transmitterblock and the 16-bit receiver block. The input reference clock operates at156 MHz.

Fujitsu Microelectronics Inc.

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